NXP Semiconductors UJA1132HW/3V3Y
- Part No.:
- UJA1132HW/3V3Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Power Management - Specialized
- Package:
- 48-TQFP Exposed Pad
- Datasheet:
-
UJA1132HW/3V3Y.pdf
- Description:
- IC TRANSCEIVER
- Quantity:
- Payment:

- Shipping:

Inventory:1,470
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Product details
Overview
UJA1132HW/3V3Y from NXP Semiconductors is a buck/boost System Basis Chip (SBC) for automotive ECUs, integrating a 3.3 V/500 mA LDO regulator (V1), ISO 11898-2/6-compliant HS-CAN transceiver supporting up to 2 Mbit/s CAN FD data fields, dual LIN 2.x transceivers, and a configurable SMPS with automatic buck/boost mode selection. It delivers fail-safe operation via watchdog, limp-home outputs (HVIO2–HVIO4), and non-volatile configuration memory - deployed in engine control modules requiring robust low-voltage resilience down to 2 V battery input.
For engineers reviewing the UJA1132HW/3V3Y datasheet, UJA1132HW/3V3Y pinout, UJA1132HW/3V3Y application, or UJA1132HW/3V3Y equivalent, this page provides verified technical context on its dual-LIN/CAN SBC architecture, SMPS pre-regulator behavior, HVIO diagnostic capabilities, and automotive-grade power management modes (Standby/Sleep/Normal).
Technical Context
The UJA1132HW/3V3Y implements a fully integrated buck-boost SMPS that automatically selects operating mode based on BAT voltage and load, enabling uninterrupted microcontroller supply during battery dips as low as 2 V. Its V1 regulator delivers 3.3 V ±2 % at 500 mA with undervoltage reset and reverse-current clamping below 6 V.
This variant includes two LIN transceivers compliant with SAE J2602 and LIN 2.x, an ISO 11898-2:201x/6:2013 HS-CAN transceiver with CAN FD-passive partial networking support, and eight HVIOs configurable as high-/low-side drivers or wake-up inputs - all managed via 16-/24-/32-bit SPI with non-volatile configuration storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output | 3.3 V ±2 %, 500 mA - powers microcontroller with transient load capability and undervoltage reset detection |
| SMPS Mode | Automatic buck/boost selection - sustains V1 during battery dips to 2 V without external semiconductors |
| CAN Data Rate | Up to 2 Mbit/s in CAN FD data field - meets ISO 11898-2:201x timing symmetry requirements |
| LIN Channels | Dual LIN 2.x transceivers - compliant with SAE J2602 and backward-compatible with LIN 1.3 |
| HVIO Count | 8 general-purpose high-voltage I/Os - individually configurable as HS/LS drivers or wake-up inputs with open-load diagnostics |
| Operating Modes | Normal, Standby (V1 active), Sleep (V1 off), Off, Overload, Reset, FSP - controlled via SPI and hardware events |
| Package | HTQFP48 (10 mm × 10 mm) - thermally enhanced with exposed die pad connected to GND |
Pinout & Package
UJA1132HW/3V3Y uses the HTQFP48 package (SOT1181-2), 10 mm × 10 mm × 1.0 mm body with exposed die pad internally connected to GND (pins 4 and 23). Thermal performance is enhanced via PCB copper area under the pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 3.3 V regulated output; enables microcontroller operation in Standby mode; shut down in Sleep mode |
| VCAN | CAN transceiver supply input | 5 V dedicated supply for HS-CAN transceiver; isolates CAN logic from V1 domain |
| CANH / CANL | CAN bus differential interface | ISO 11898-2-compliant physical layer; supports CAN FD fast phase up to 2 Mbit/s |
| LIN1 / LIN2 | Two independent LIN bus interfaces | Dual LIN 2.x transceivers with integrated slave termination and optimized EMC emission |
| HVIO1–HVIO8 | High-voltage I/O bank (2 banks of 4) | Configurable as HS/LS drivers or wake-up inputs; supports limp-home signals (HVIO2–HVIO4) and cyclic contact monitoring |
| RSTN | Bidirectional reset pin | Active-low reset I/O referenced to V1; triggered by watchdog overflow or V1 undervoltage |
| INTN1 / INTN2 | Interrupt outputs | INTN1 reports all interrupts; INTN2 reports only high-priority events (e.g., overtemperature, CAN diagnostics) |
| LIMP | Limp-home activation output | Drives external fail-safe hardware; activated in Overload/FSP modes or via SPI-controlled limp-home function |
Key Features
| Feature | Design Value |
|---|---|
| SMPS pre-regulation | Reduces ripple and improves transient response at V1/V2 by decoupling regulation from battery fluctuations |
| CAN FD-passive partial networking | Enables Sleep mode retention during CAN FD traffic - prevents false wake-ups while maintaining classic CAN compatibility |
| Non-volatile configuration memory | Stores power-on behavior, limp-home settings, and wake-up thresholds - eliminates boot-time reconfiguration |
| 8-channel HVIO diagnostics | Provides open-load detection, short-circuit protection, and loss-of-ground/loss-of-battery proofing per pin |
| Multi-mode power management | Supports <100 µA Sleep current and <500 µA Standby current - extends ECU battery life in key-off states |
| Integrated A/D battery monitor | 10-bit ADC with dual-channel measurement (BAT/BATSENSE) - enables precise undervoltage/overvoltage shutdown decisions |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Real-time engine timing and fuel injection control under wide battery voltage range (6–16 V), including cold-crank conditions down to 2 V. IC Role / Device Role / Timing Role: Central SBC providing regulated 3.3 V power, CAN FD communication to powertrain network, dual LIN for sensor actuation, and HVIO-driven injector drivers. Use Value: Maintains microcontroller operation during cranking dips via boost-mode SMPS; prevents system reset and preserves calibration data. |
Use Scenario: Integrated lighting, door lock, and window control with distributed LIN nodes and centralized CAN gateway functionality. IC Role / Device Role / Timing Role: Power manager and bus interface - supplies MCU, handles LIN slave communication, routes CAN messages, and drives HVIO-based relays/latches. Use Value: Dual LIN channels reduce wiring complexity; HVIO open-load diagnostics enable predictive maintenance of door lock actuators. |
| Advanced Driver Assistance System (ADAS) Sensor Hub | Electric Power Steering (EPS) ECU |
Use Scenario: Aggregating radar, camera, and ultrasonic sensor data in a compact module with strict EMC and thermal constraints. IC Role / Device Role / Timing Role: System basis chip delivering clean 3.3 V power, CAN FD backbone connectivity, and LIN links to peripheral sensors - managed via SPI diagnostics. Use Value: Excellent EMC performance and ±6 kV HBM ESD protection on CAN/LIN pins ensure reliable operation in noisy vehicle environments. |
Use Scenario: High-reliability motor control where failure must trigger safe torque reduction and mechanical fallback. IC Role / Device Role / Timing Role: Safety-critical SBC supplying MCU, monitoring battery health, driving limp-home outputs (HVIO2–HVIO4), and asserting EN pin on fault. Use Value: Configurable limp-home waveforms (100 Hz/10 %, 1.25 Hz/50 %) directly activate mechanical steering fallback mechanisms without software intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/5V0 | Same package and feature set, but V1 output is 5 V instead of 3.3 V; identical SMPS, CAN, LIN, HVIO, and diagnostic capabilities | Required when interfacing with 5 V microcontrollers or legacy peripherals; not suitable for 3.3 V-only designs without level-shifting | Select UJA1132HW/5V0 only if target MCU requires 5 V supply - no PCB changes needed, but verify V1 voltage compatibility with downstream logic |
| UJA1132HW/FD/3V/4 | Adds CAN FD-passive partial networking and four HVIOs configured for wake-up; removes HVIO5–HVIO8; same 3.3 V V1 and dual LIN | Optimized for networks mixing CAN FD and classic CAN where selective sleep is critical; reduced HVIO count limits multi-output fail-safe use cases | Choose UJA1132HW/FD/3V/4 when CAN FD traffic volume demands guaranteed Sleep mode retention - confirm HVIO count suffices for limp-home and driver needs |
Compared with UJA1132HW/3V3Y, UJA1132HW/5V0 offers identical functionality except V1 voltage, making it a direct substitution only for 5 V systems; UJA1132HW/FD/3V/4 trades HVIO count for CAN FD-passive networking, prioritizing bus efficiency over output flexibility in mixed-protocol networks.
Availability
UJA1132HW/3V3Y is available at Aetrix Electronics and suitable for automotive engine control units, body control modules, ADAS sensor hubs, and electric power steering ECUs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for UJA1132HW/3V3Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade power management and communication ICs.
The UJA113x series was designed specifically for next-generation automotive ECUs needing integrated buck/boost power conversion, dual-bus (CAN + LIN) connectivity, and fail-safe system control - targeting ASIL-B compatible architectures.
FAQ
What is the minimum battery voltage at which UJA1132HW/3V3Y can sustain microcontroller operation?
UJA1132HW/3V3Y maintains 3.3 V output to the microcontroller down to 2 V battery input using its boost-mode SMPS. This capability is validated under defined load conditions and enables uninterrupted operation during cold-crank events. The actual lowest sustainable voltage depends on output load and thermal conditions, but 2 V is the specified functional limit per NXP documentation.
Does UJA1132HW/3V3Y support CAN FD communication in both normal and partial networking modes?
UJA1132HW/3V3Y supports CAN FD data fields up to 2 Mbit/s in active communication but does not implement CAN FD-passive partial networking. That feature is exclusive to UJA113xFD/x variants. In Sleep mode, UJA1132HW/3V3Y will wake on any CAN activity - including CAN FD frames - unlike FD-passive variants which ignore CAN FD traffic during Sleep.
How many LIN transceivers does UJA1132HW/3V3Y integrate, and are they independently configurable?
UJA1132HW/3V3Y integrates two fully independent LIN 2.x transceivers (LIN1 and LIN2), each compliant with SAE J2602 and backward-compatible with LIN 1.3. They support separate bus connections, individual termination, and independent SPI-controlled configuration - enabling simultaneous communication with two distinct LIN subnetworks.
Can the HVIO pins on UJA1132HW/3V3Y be used for both driving loads and sensing wake-up events?
Yes - all eight HVIO pins on UJA1132HW/3V3Y are individually configurable as high-side drivers, low-side drivers, or wake-up inputs via SPI. Each supports selectable wake-up edge (rising/falling), ratiometric or absolute threshold detection, and wake-source reporting. Open-load diagnostics and short-circuit protection apply in all configurations.
What is the role of the LIMP pin on UJA1132HW/3V3Y, and how is it activated?
The LIMP pin on UJA1132HW/3V3Y is a dedicated fail-safe output that activates during Overload mode or Forced Sleep Preparation (FSP) to drive external hardware into a safe state. It can also be asserted via SPI-controlled limp-home function using HVIO2 (static), HVIO3 (100 Hz/10 %), or HVIO4 (1.25 Hz/50 %) - providing three distinct waveform options for mechanical fallback activation.
Is the SMPS in UJA1132HW/3V3Y capable of powering external loads beyond the internal regulators?
Yes - the SMPS output (VSMPS) of UJA1132HW/3V3Y can directly supply external loads such as LED chains or auxiliary circuitry. It operates as a pre-regulator for V1 and V2 but may be configured in Pass-through mode for lowest quiescent current and immediate full output current capability, making it suitable for energy-efficient auxiliary power delivery.
UJA1132HW/3V3Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 48-TQFP Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Applications:
- -
- Current - Supply:
- 2.8mA
- Voltage - Supply:
- 2V ~ 28V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-HTQFP (10x10)
UJA1132HW/3V3Y FAQ
1.How can I place an order for UJA1132HW/3V3Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1132HW/3V3Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1132HW/3V3Y reliable?
The price and inventory of UJA1132HW/3V3Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1132HW/3V3Y is usually 5 days.
3.What payment methods are accepted for UJA1132HW/3V3Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1132HW/3V3Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1132HW/3V3Y?
UJA1132HW/3V3Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1132HW/3V3Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1132HW/3V3Y?
For technical support, including UJA1132HW/3V3Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1132HW/3V3Y requirements.
6.How does Aetrix verify that UJA1132HW/3V3Y is sourced from the original manufacturer or authorized distributors?
All UJA1132HW/3V3Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1132HW/3V3Y meets industry standards.
7.What is the process for return or replacement of UJA1132HW/3V3Y?
All UJA1132HW/3V3Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1132HW/3V3Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1132HW/3V3Y part is unused and in its original packaging.
Return procedure for UJA1132HW/3V3Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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