NXP Semiconductors UJA1132HW/FD/5V/0Y
- Part No.:
- UJA1132HW/FD/5V/0Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Power Management - Specialized
- Package:
- 48-TQFP Exposed Pad
- Datasheet:
-
UJA1132HW/FD/5V/0Y.pdf
- Description:
- BUCK/BOOST HS-CAN/DUAL LIN SYSTE
- Quantity:
- Payment:

- Shipping:

Inventory:1,400
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Product details
Overview
UJA1132HW/FD/5V/0Y from NXP Semiconductors is a buck/boost System Basis Chip (SBC) for automotive ECUs, integrating a 5 V/500 mA LDO regulator, ISO 11898-2/6-compliant HS-CAN transceiver supporting CAN FD up to 2 Mbit/s, dual LIN transceivers, and CAN FD-passive partial networking. It delivers fail-safe operation via watchdog, limp-home outputs (HVIO2–HVIO4), and battery monitoring with 10-bit ADC. Used in engine control modules requiring robust low-voltage operation down to 2 V during cranking.
For engineers reviewing the UJA1132HW/FD/5V/0Y datasheet, UJA1132HW/FD/5V/0Y pinout, UJA1132HW/FD/5V/0Y application, or UJA1132HW/FD/5V/0Y equivalent, this page provides verified technical context, validated pin functions, confirmed automotive power management features, and real-world use cases for ECU design under ISO 7637-3 transient stress and partial-networking sleep requirements.
Technical Context
The UJA1132HW/FD/5V/0Y implements a single-coil buck-boost SMPS that automatically switches between Buck (VIN > VOUT) and Boost (VIN < VOUT) modes to sustain 5 V/500 mA output down to 2 V battery input. Its CAN transceiver complies with ISO 11898-2:201x and ISO 11898-6:2013, enabling CAN FD-passive selective wake-up-ignoring CAN FD traffic in Sleep mode while responding to classic CAN frames.
This variant supports dual LIN 2.x transceivers (LIN1/LIN2), two-channel battery A/D monitoring (BAT/BATSENSE), and four HVIO pins (HVIO1–HVIO4) configured as high-side drivers or wake-up inputs. Non-volatile memory stores limp-home behavior, wake thresholds, and SPI-configurable SMPS pre-regulator voltage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Regulator V1 | 5 V ±2 %, 500 mA output; powers microcontroller with undervoltage reset at 90 % nominal (4.5 V) by default. |
| SMPS Mode | Buck/Boost auto-switching; sustains V1 during battery dips to 2 V, eliminating need for external boost IC in cold-crank scenarios. |
| CAN Data Rate | Up to 2 Mbit/s in CAN FD fast phase; meets ISO 11898-2:201x timing symmetry for reliable FD communication. |
| CAN Partial Networking | ISO 11898-6:2013 compliant with CAN FD-passive; prevents false wake-ups during CAN FD bus activity in Sleep mode. |
| LIN Channels | Dual LIN 2.x transceivers (LIN1 + LIN2); integrated slave termination and SAE J2602 compliance for body control networks. |
| Battery Monitoring | 10-bit ADC with ±300 mV accuracy at 20 V full scale; measures both BAT and BATSENSE for polarity-diode-aware voltage sensing. |
| Package | HTQFP48 (10 mm × 10 mm); exposed die pad thermally connected to GND for enhanced heat dissipation in under-hood environments. |
Pinout & Package
HTQFP48 package with 48-pin thermal-enhanced quad flat layout; exposed die pad internally tied to GND (pins 4, 23) and requires PCB ground connection for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 5 V ±2 % regulated output; powers MCU core; shuts off in Sleep mode to reduce quiescent current. |
| VCAN | CAN transceiver supply | 5 V dedicated supply for HS-CAN PHY; isolates CAN noise from V1 domain. |
| CANH / CANL | CAN bus differential pair | ISO 11898-2-compliant physical layer interface; ±40 V short-circuit proof with IEC 61000-4-2 ESD protection. |
| LIN1 / LIN2 | Local Interconnect Network buses | Dual LIN 2.x physical interfaces; support independent network domains (e.g., lighting + HVAC). |
| HVIO1–HVIO4 | Configurable high-voltage I/Os | Individually set as HS drivers, LS drivers, or wake-up inputs; support limp-home signals (HVIO2 static, HVIO3 100 Hz, HVIO4 1.25 Hz). |
| LIMP | Limp-home activation output | Asserted LOW during Overload mode or FSP; drives external hardware for safe degradation (e.g., reduced fan speed). |
| RSTN | Bidirectional reset pin | Open-drain output referenced to V1; triggered by V1 undervoltage or watchdog overflow; configurable pulse length. |
| INTN1 / INTN2 | Interrupt outputs | INTN1 reports all events; INTN2 reserved for high-priority alerts (e.g., overtemperature, CAN diagnostics). |
Key Features
| Feature | Design Value |
|---|---|
| CAN FD-passive partial networking | Enables Sleep mode retention during CAN FD traffic-prevents bus errors from legacy CAN nodes unaware of FD frames. |
| Auto-switching buck-boost SMPS | Single external coil supports seamless transition between Buck and Boost; maintains 5 V/500 mA down to 2 V battery without external MOSFETs or controllers. |
| Dual LIN transceivers with integrated termination | Reduces BOM count by eliminating external LIN resistors; supports independent LIN domains with SAE J2602 EMC compliance. |
| Four programmable HVIOs with limp-home capability | HVIO2–HVIO4 generate standardized limp-home waveforms (static, 100 Hz, 1.25 Hz); configurable via non-volatile memory for application-specific fail-safe behavior. |
| Two-channel battery A/D monitoring | Simultaneously monitors raw battery (BAT) and post-diode voltage (BATSENSE); enables accurate state-of-charge estimation despite polarity protection losses. |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Cold-cranking operation where battery voltage drops below 6 V for extended periods. IC Role / Device Role / Timing Role: System Basis Chip providing regulated 5 V power, CAN FD communication, and dual LIN connectivity while sustaining MCU operation via boost-mode SMPS. Use Value: Eliminates need for external boost converter; ensures uninterrupted ECU function during 2 V battery dips per ISO 16750-2 Pulse 4. | Use Scenario: Multi-domain vehicle body network with separate LIN clusters for lighting, door modules, and HVAC. IC Role / Device Role / Timing Role: Dual-LIN transceiver hub with CAN gateway functionality and partial-networking sleep for energy-efficient always-on monitoring. Use Value: Reduces standby current to <100 µA while maintaining wake-up responsiveness across two independent LIN buses. |
| Advanced Driver Assistance System (ADAS) Sensor Hub | Electric Power Steering (EPS) ECU |
Use Scenario: Centralized sensor aggregation node communicating with radar, camera, and ultrasonic sensors via LIN and CAN. IC Role / Device Role / Timing Role: Power manager and bus interface with CAN FD-passive wake-up-staying asleep during high-bandwidth CAN FD sensor data bursts. Use Value: Prevents spurious wake-ups from CAN FD traffic, extending sleep duration and reducing system-level power consumption by >30 %. | Use Scenario: Safety-critical EPS ECU requiring fail-operational behavior during voltage transients or thermal overload. IC Role / Device Role / Timing Role: Fault-tolerant SBC delivering limp-home outputs (HVIO2–HVIO4), overtemperature shutdown, and watchdog-managed reset sequencing. Use Value: Activates standardized limp-home signals on dedicated pins to maintain steering assist at reduced torque during fault conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/5V0 | Lacks CAN FD-passive partial networking; no ISO 11898-6 support; identical SMPS, LDO, and HVIO specs. | Not suitable for CAN FD networks requiring selective wake-up; limited to classic CAN-only architectures. | Select when CAN FD is unused and cost optimization is prioritized over future-proofing. |
| TLE9471-3ES | Single LIN channel; no dual-LIN support; includes embedded 32-bit safety monitor; different SPI register map and fault reporting. | Targeted at ASIL-B systems with higher functional safety requirements; lacks native CAN FD-passive capability. | Choose for ISO 26262 ASIL-B designs needing integrated safety controller, not for dual-LIN/CAN FD hybrid networks. |
Compared with UJA1132HW/5V0, the UJA1132HW/FD/5V/0Y adds CAN FD-passive wake-up without changing pinout or power specs-enabling drop-in upgrade in existing HTQFP48 layouts. Versus TLE9471-3ES, it trades ASIL-B safety monitoring for dual-LIN and CAN FD network flexibility in non-safety-critical body domains.
Availability
UJA1132HW/FD/5V/0Y is available at Aetrix Electronics and suitable for automotive engine control units, body control modules, ADAS sensor hubs, and electric power steering ECUs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for UJA1132HW/FD/5V/0Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade power management and communication ICs.
The UJA113x product line delivers integrated System Basis Chips for next-generation automotive ECUs, combining buck-boost power conversion, CAN FD, dual LIN, and fail-safe control to simplify ECU architecture and reduce system-level BOM cost.
FAQ
What is the minimum battery voltage at which UJA1132HW/FD/5V/0Y can sustain 5 V output?
The UJA1132HW/FD/5V/0Y sustains its 5 V/500 mA V1 output down to 2 V battery input using its integrated boost-mode SMPS. This capability is validated per ISO 16750-2 Pulse 4 test conditions and enables uninterrupted microcontroller operation during severe cold-cranking events. The actual lowest operational voltage depends on load current but remains functional at 2 V with typical ECU loads.
Does UJA1132HW/FD/5V/0Y support CAN FD communication in active mode?
Yes, UJA1132HW/FD/5V/0Y supports CAN FD active communication up to 2 Mbit/s in the data field, compliant with ISO 11898-2:201x timing requirements. Its CAN transceiver implements loop delay symmetry specifications required for reliable FD fast-phase operation, making it suitable for high-throughput automotive gateways and domain controllers.
How many LIN transceivers does UJA1132HW/FD/5V/0Y integrate?
UJA1132HW/FD/5V/0Y integrates two fully compliant LIN 2.x transceivers (LIN1 and LIN2), each with built-in slave termination and SAE J2602 qualification. These operate independently, allowing connection to separate LIN subnetworks such as lighting and seat control without external transceivers.
What is the function of the LIMP pin on UJA1132HW/FD/5V/0Y?
The LIMP pin on UJA1132HW/FD/5V/0Y is a dedicated fail-safe output that asserts LOW during Overload or Forced Sleep Preparation (FSP) modes. It directly drives external hardware-such as reduced-power motor drivers or warning indicators-to implement application-specific limp-home behavior without MCU intervention.
Is UJA1132HW/FD/5V/0Y pin-compatible with other UJA113x variants in HTQFP48?
Yes, UJA1132HW/FD/5V/0Y uses the same HTQFP48 package (SOT1181-2) and identical pinout as all UJA113x family members, including UJA1132HW/5V0 and UJA1131HW/FD/5V/4. This allows direct replacement in existing PCB layouts when upgrading to CAN FD-passive functionality without board revision.
UJA1132HW/FD/5V/0Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 48-TQFP Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Applications:
- -
- Current - Supply:
- 2.8mA
- Voltage - Supply:
- 2V ~ 28V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-HTQFP (10x10)
UJA1132HW/FD/5V/0Y FAQ
1.How can I place an order for UJA1132HW/FD/5V/0Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1132HW/FD/5V/0Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1132HW/FD/5V/0Y reliable?
The price and inventory of UJA1132HW/FD/5V/0Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1132HW/FD/5V/0Y is usually 5 days.
3.What payment methods are accepted for UJA1132HW/FD/5V/0Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1132HW/FD/5V/0Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1132HW/FD/5V/0Y?
UJA1132HW/FD/5V/0Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1132HW/FD/5V/0Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1132HW/FD/5V/0Y?
For technical support, including UJA1132HW/FD/5V/0Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1132HW/FD/5V/0Y requirements.
6.How does Aetrix verify that UJA1132HW/FD/5V/0Y is sourced from the original manufacturer or authorized distributors?
All UJA1132HW/FD/5V/0Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1132HW/FD/5V/0Y meets industry standards.
7.What is the process for return or replacement of UJA1132HW/FD/5V/0Y?
All UJA1132HW/FD/5V/0Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1132HW/FD/5V/0Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1132HW/FD/5V/0Y part is unused and in its original packaging.
Return procedure for UJA1132HW/FD/5V/0Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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