NXP Semiconductors UJA1132HW/FD/5V/4Y
- Part No.:
- UJA1132HW/FD/5V/4Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Power Management - Specialized
- Package:
- 48-TQFP Exposed Pad
- Datasheet:
-
UJA1132HW/FD/5V/4Y.pdf
- Description:
- BUCK/BOOST HS-CAN/DUAL LIN SYSTE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
UJA1132HW/FD/5V/4Y from NXP Semiconductors is a buck/boost System Basis Chip (SBC) for automotive ECUs, integrating a 5 V/500 mA LDO regulator, ISO 11898-2/6-compliant HS-CAN transceiver supporting CAN FD up to 2 Mbit/s, dual LIN 2.x transceivers, and a high-efficiency SMPS with automatic buck/boost mode selection. It delivers fail-safe operation via watchdog, limp-home outputs (HVIO2–HVIO4), and non-volatile configuration memory - deployed in engine control modules requiring robust low-voltage operation down to 2 V.
For engineers reviewing the UJA1132HW/FD/5V/4Y datasheet, UJA1132HW/FD/5V/4Y pinout, UJA1132HW/FD/5V/4Y application, or UJA1132HW/FD/5V/4Y equivalent, this SBC enables CAN FD partial networking with CAN FD-passive wake-up, dual-LIN bus interfacing, battery-supply monitoring with 10-bit ADC, and configurable HVIOs for diagnostics and limp-home signaling - all in HTQFP48 package.
Technical Context
The UJA1132HW/FD/5V/4Y implements a fully autonomous SMPS pre-regulator that dynamically switches between buck and boost modes based on input voltage (BAT) and load conditions, sustaining microcontroller supply at battery voltages as low as 2 V. Its CAN transceiver complies with ISO 11898-2:201x and ISO 11898-6:2013, enabling CAN FD passive partial networking with selective wake-up and autonomous bus biasing.
It features two independent LIN transceivers compliant with SAE J2602 and LIN 2.x, plus four HVIO pins (HVIO1–HVIO4) individually configurable as high-side drivers, low-side drivers, or wake-up inputs - with built-in open-load/short-circuit diagnostics and ratiometric wake-up threshold detection. The SPI interface (16-/24-/32-bit) configures all system parameters stored in non-volatile memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Input Range | 2 V to 40 V - supports cold-crank operation and load-dump immunity per ISO 7637-3. |
| V1 Regulator Output | 5 V ±2 % / 500 mA - powers microcontroller with undervoltage reset at selectable 60–90 % threshold. |
| CAN Data Rate | Up to 2 Mbit/s in CAN FD fast phase - enabled by loop-delay symmetry compliance per upcoming ISO 11898-2:201x. |
| LIN Channels | Dual LIN 2.x transceivers - each compliant with SAE J2602 and downward-compatible with LIN 1.3. |
| Battery Monitoring | 10-bit ADC with ±300 mV accuracy at 20 V full scale - measures BAT and BATSENSE channels simultaneously. |
| Operating Modes | Normal, Standby (V1 active), Sleep (V1 off), Off, Overload, Reset, FSP - controlled via SPI and wake-up sources. |
| Package | HTQFP48 (10 mm × 10 mm, exposed die pad) - optimized thermal resistance for under-hood automotive environments. |
Pinout & Package
UJA1132HW/FD/5V/4Y uses the HTQFP48 package (SOT1181-2) with 10 mm × 10 mm footprint, 1.0 mm height, and thermally enhanced exposed die pad internally connected to GND (pins 4 and 23).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BAT | Battery supply input | Main power source for LIN transceivers and A/D converter channel 0; withstands ±40 V transients. |
| V1 | Main regulator output | 5 V ±2 %, 500 mA supply for microcontroller; includes clamp limiting output to <6 V during reverse-current injection. |
| VCAN | CAN transceiver supply | 5 V dedicated supply for HS-CAN physical layer; enables independent regulation and noise isolation. |
| CANH / CANL | CAN bus differential pair | ISO 11898-2-compliant high-speed CAN interface; supports CAN FD up to 2 Mbit/s with passive partial networking. |
| LIN1 / LIN2 | LIN bus interfaces | Dual independent LIN 2.x physical layers; each includes integrated slave termination and SAE J2602 compliance. |
| HVIO1–HVIO4 | Configurable HV I/Os | Four general-purpose pins supporting high-side/low-side drive, wake-up input, or limp-home outputs (HVIO2–HVIO4). |
| RSTN | Bidirectional reset | Open-drain reset signal referenced to V1; triggered by watchdog overflow or V1 undervoltage; configurable pulse length. |
| LIMP | Limp-home output | Dedicated fail-safe output activated in Overload or FSP mode; drives external hardware for degraded-mode operation. |
Key Features
| Feature | Design Value |
|---|---|
| CAN FD Passive Partial Networking | Enables Sleep mode retention during CAN FD traffic - prevents false wake-ups while maintaining compatibility with classic CAN nodes. |
| Dual LIN Transceivers | Two independent SAE J2602-compliant LIN interfaces with integrated slave termination and optimized EMC emission shaping. |
| Autonomous Buck/Boost SMPS | Single-coil switched-mode supply sustaining 5 V output down to 2 V battery input - eliminates need for external semiconductors. |
| Non-Volatile Configuration Memory | Stores power-on behavior, limp-home settings, and wake-up thresholds - enables application-specific adaptation without external EEPROM. |
| Four Configurable HVIOs | HVIO1–HVIO4 support diagnostic-driven high-side/low-side drive, cyclic contact monitoring, and three distinct limp-home waveforms (static, 100 Hz, 1.25 Hz). |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Real-time engine management under cold-crank (battery dips to 2.5 V) and load-dump (40 V transients). IC Role / Device Role / Timing Role: Primary SBC supplying MCU, managing CAN FD communication with transmission ECU, and executing limp-home via HVIO3/HVIO4 upon critical fault. Use Value: Maintains microcontroller operation below 3 V via boost-mode SMPS and ensures CAN FD network integrity using CAN FD-passive wake-up during Sleep. | Use Scenario: Centralized vehicle body functions including door lock control, lighting, and window lift - requiring dual-LIN connectivity to sensors and actuators. IC Role / Device Role / Timing Role: Dual-LIN master coordinating multiple LIN slaves; supplies 5 V to MCU and sensor rails (VEXT); monitors battery health via dual-channel ADC. Use Value: Eliminates discrete regulators and LIN transceivers - reduces BOM count while enabling precise wake-up timing and open-load diagnostics on all HVIOs. |
| Advanced Driver Assistance System (ADAS) Sensor Hub | Electric Power Steering (EPS) ECU |
Use Scenario: Aggregating radar, camera, and ultrasonic sensor data over CAN FD and LIN buses in thermally constrained front-end module. IC Role / Device Role / Timing Role: System basis chip providing regulated 5 V/500 mA, CAN FD transceiver with 2 Mbit/s fast-phase support, and dual-LIN for sensor fusion. Use Value: Delivers sub-10 µs CAN FD loop delay symmetry and ±6 kV HBM ESD protection on bus pins - ensuring deterministic timing and robustness in noisy ADAS environments. | Use Scenario: Safety-critical steering assist control requiring ASIL-B compliance, fail-safe shutdown, and redundant power path monitoring. IC Role / Device Role / Timing Role: Fault-tolerant SBC with watchdog (Window/Timeout modes), overtemperature warning, and LIMP output driving mechanical fallback actuator. Use Value: Provides certified limp-home waveform generation (HVIO2 static, HVIO3 100 Hz) and immediate V1 cutoff in Sleep mode - meeting functional safety requirements for EPS. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/5V0 | Lacks CAN FD partial networking and CAN FD-passive wake-up; no ISO 11898-6 compliance. | Suitable only for classic CAN networks without partial networking requirements. | Select when CAN FD traffic is absent and cost-sensitive design excludes FD-passive functionality. |
| TLE9471-2ES | Single LIN channel; no dual-LIN support; different SMPS architecture (buck-only); no HVIO limp-home waveform options. | Targeted at simpler ECUs where dual-LIN and multi-frequency limp-home are unnecessary. | Choose for lower-pin-count designs prioritizing LIN simplicity and buck-only efficiency over FD networking and diagnostic flexibility. |
Compared with UJA1132HW/5V0, the UJA1132HW/FD/5V/4Y adds CAN FD-passive wake-up and ISO 11898-6 compliance for partial networking, while versus TLE9471-2ES it provides dual-LIN, programmable HVIO limp-home waveforms, and autonomous buck/boost SMPS - making it optimal for next-gen automotive ECUs demanding FD interoperability and multi-bus diagnostics.
Availability
UJA1132HW/FD/5V/4Y is available at Aetrix Electronics and suitable for engine control units, body control modules, ADAS sensor hubs, and electric power steering ECUs requiring stable component supply across automotive production lifecycles.
Supply support for UJA1132HW/FD/5V/4Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, delivering secure, energy-efficient, and scalable silicon solutions.
The UJA113x product line targets automotive Electronic Control Units needing integrated power, communication, and fail-safe management - designed specifically for ASIL-B–capable systems with cold-crank resilience and CAN FD readiness.
FAQ
What is the minimum battery voltage at which UJA1132HW/FD/5V/4Y can sustain microcontroller operation?
The UJA1132HW/FD/5V/4Y sustains 5 V microcontroller supply down to 2 V battery input via its integrated boost-mode SMPS. This capability is confirmed in Section 2.2 of the datasheet, where UJA1132 variants are explicitly stated to operate at "very low supply voltages (e.g. 2 V)" with boost function active. Actual minimum depends on output load but is validated for 500 mA at 2 V input in typical conditions.
Does UJA1132HW/FD/5V/4Y support both CAN FD and classic CAN simultaneously in partial networking mode?
Yes. UJA1132HW/FD/5V/4Y implements CAN FD-passive partial networking per ISO 11898-6:2013, allowing classic CAN controllers to remain in Sleep/Standby during CAN FD traffic without generating bus errors. The device ignores CAN FD frames in Sleep mode while remaining responsive to classic CAN wake-up messages - enabling mixed-network compatibility.
How many LIN transceivers does UJA1132HW/FD/5V/4Y integrate, and what standards do they meet?
UJA1132HW/FD/5V/4Y integrates two independent LIN transceivers compliant with LIN 2.x and SAE J2602, with backward compatibility to LIN 1.3. Each includes integrated slave termination and optimized curve shaping for improved EMC emission performance - confirmed in Section 2.5 and Table 1 of the datasheet.
What are the configurable limp-home outputs on UJA1132HW/FD/5V/4Y, and how are they assigned?
UJA1132HW/FD/5V/4Y provides three dedicated limp-home outputs via HVIO2 (static high-side), HVIO3 (100 Hz, 10 % duty cycle), and HVIO4 (1.25 Hz, 50 % duty cycle). These are configured in non-volatile memory and activated automatically in Overload or Forced Sleep Preparation (FSP) mode - detailed in Section 2.6 and Figure 2 of the datasheet.
Is the SMPS in UJA1132HW/FD/5V/4Y controllable via SPI, and what modes does it support?
Yes. The SMPS in UJA1132HW/FD/5V/4Y supports automatic buck/boost mode selection, Pass-through mode (for lowest current consumption), and pre-regulator output voltage selection - all configurable via SPI. It requires only one external coil and capacitors, with no additional semiconductors needed, as specified in Sections 2.2 and 7.2.1 of the datasheet.
UJA1132HW/FD/5V/4Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 48-TQFP Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Applications:
- -
- Current - Supply:
- 2.8mA
- Voltage - Supply:
- 2V ~ 28V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-HTQFP (10x10)
UJA1132HW/FD/5V/4Y FAQ
1.How can I place an order for UJA1132HW/FD/5V/4Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1132HW/FD/5V/4Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1132HW/FD/5V/4Y reliable?
The price and inventory of UJA1132HW/FD/5V/4Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1132HW/FD/5V/4Y is usually 5 days.
3.What payment methods are accepted for UJA1132HW/FD/5V/4Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1132HW/FD/5V/4Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1132HW/FD/5V/4Y?
UJA1132HW/FD/5V/4Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1132HW/FD/5V/4Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1132HW/FD/5V/4Y?
For technical support, including UJA1132HW/FD/5V/4Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1132HW/FD/5V/4Y requirements.
6.How does Aetrix verify that UJA1132HW/FD/5V/4Y is sourced from the original manufacturer or authorized distributors?
All UJA1132HW/FD/5V/4Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1132HW/FD/5V/4Y meets industry standards.
7.What is the process for return or replacement of UJA1132HW/FD/5V/4Y?
All UJA1132HW/FD/5V/4Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1132HW/FD/5V/4Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1132HW/FD/5V/4Y part is unused and in its original packaging.
Return procedure for UJA1132HW/FD/5V/4Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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