NXP Semiconductors UJA1135HW/5V0Y
- Part No.:
- UJA1135HW/5V0Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Power Management - Specialized
- Package:
- 48-TQFP Exposed Pad
- Datasheet:
-
UJA1135HW/5V0Y.pdf
- Description:
- IC TRANSCEIVER
- Quantity:
- Payment:

- Shipping:

Inventory:1,500
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Product details
Overview
UJA1135HW/5V0Y from NXP Semiconductors is a buck/boost System Basis Chip (SBC) for automotive ECUs, integrating a 5 V/500 mA LDO (V1), ISO 11898-2/6-compliant HS-CAN transceiver supporting up to 2 Mbit/s CAN FD data fields, dual LIN transceivers, and a buck-boost SMPS with low-current boost capability for microcontroller memory retention down to 2 V battery supply. It operates in Standby/Sleep modes with full wake-up via CAN, LIN or HVIO pins.
For engineers reviewing the UJA1135HW/5V0Y datasheet, UJA1135HW/5V0Y pinout, UJA1135HW/5V0Y application, or UJA1135HW/5V0Y equivalent, this page delivers verified technical context, exact pin functions, real-world automotive use cases, and validated alternative parts - all grounded in NXP's official UJA113x product data sheet Rev. 2 (2016).
Technical Context
The UJA1135HW/5V0Y implements a dual-mode switched-mode power supply (SMPS) that automatically selects Buck or Boost operation based on input voltage and load; its boost stage supplies only volatile microcontroller memory-not core logic-down to 2 V battery, with limited output current. It integrates two LIN transceivers compliant with SAE J2602 and LIN 2.x, plus a high-speed CAN transceiver meeting ISO 11898-2:201x and ISO 11898-6:2013 for partial networking.
Its system controller supports five operating modes (Off, Standby, Normal, Sleep, Overload) with non-volatile configuration of power-on behavior and limp-home outputs. The device includes four configurable HVIOs (HS/LS/wake-up), a 10-bit battery A/D converter, watchdog with Window/Timeout modes, and SPI interface (16-/24-/32-bit) for register-level control and diagnostics.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output | 5 V ±2 %, 500 mA max - powers microcontroller core with undervoltage reset at selectable 60–90 % threshold. |
| SMPS Mode | Buck/Boost with single external coil - automatic mode selection; boost supports memory retention only (not MCU core) at ≥2 V battery. |
| CAN Data Rate | Up to 2 Mbit/s in CAN FD data field - compliant with ISO 11898-2:201x and ISO 11898-6:2013 for partial networking. |
| LIN Channels | Dual LIN transceivers - SAE J2602 and LIN 2.x compliant, downward compatible with LIN 1.3, with integrated slave termination. |
| HVIO Count | 4 general-purpose high-voltage I/Os - individually configurable as HS/LS drivers or wake-up inputs; support limp-home outputs (HVIO2–HVIO4). |
| Package | HTQFP48 (10 mm × 10 mm, 1.0 mm height) - thermally enhanced with exposed die pad connected to GND. |
| Operating Temp | −40 °C to +150 °C - qualified for under-hood automotive applications per AEC-Q100 Grade 0. |
Pinout & Package
UJA1135HW/5V0Y uses the HTQFP48 package (SOT1181-2), featuring a 10 mm × 10 mm body, 1.0 mm profile, and exposed thermal pad internally tied to GND (pins 4 and 23). PCB layout requires direct connection of the pad to ground plane for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 (Pin 6) | Main microcontroller supply output | 5 V ±2 %, 500 mA regulated LDO output; disabled in Sleep mode; includes clamp limiting voltage to ≤6 V during reverse current injection. |
| VCAN (Pin 20) | CAN transceiver supply | 5 V dedicated supply for HS-CAN physical layer; enables independent biasing and noise isolation from V1. |
| RXDC / TXDC (Pins 18/19) | CAN data interface | Differential digital interface between SBC and MCU CAN controller; supports 2 Mbit/s FD data field timing. |
| LIN1 / LIN2 (Pins 24/25) | LIN bus interfaces | Two independent LIN physical layers; LIN2 is internally connected and must be left open per datasheet for UJA1135x variants. |
| HVIO1–HVIO4 (Pins 37–34) | Configurable high-voltage I/Os | Four pins individually settable as high-side/low-side drivers or wake-up inputs; support limp-home signals (HVIO2 static, HVIO3 100 Hz, HVIO4 1.25 Hz). |
| LIMP (Pin 39) | Limp-home activation output | Open-drain output asserting fault condition; driven LOW in Overload mode or via SPI-controlled limp-home function. |
| RSTN (Pin 12) | Bidirectional reset signal | Active-low reset line referenced to V1; triggered by watchdog overflow or V1 undervoltage; supports configurable pulse width. |
| SCK / SDO / SDI / SCSN (Pins 9/8/7/10) | SPI interface | Full-duplex 16-/24-/32-bit SPI for configuration, status readback, and diagnostic control; supports interrupt-driven register access. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated buck-boost SMPS | Single-coil architecture enabling automatic Buck/Boost mode switching; eliminates need for external FETs or controllers while maintaining <10 mV ripple at V1/V2. |
| Dual LIN + HS-CAN transceivers | One CAN and two LIN physical layers on-chip - reduces BOM count and board space; LIN2 is functional but internally connected (pin 25 open). |
| Non-volatile configuration memory | Stores power-on behavior, limp-home settings, and Sleep mode enable/disable state - allows field-programmable adaptation without hardware change. |
| Fail-safe limp-home outputs | Three preconfigured HVIOs (HVIO2–HVIO4) deliver distinct fault-signaling waveforms - static HIGH, 100 Hz 10 % duty, and 1.25 Hz 50 % duty - for ECU-level degradation handling. |
| Robust automotive protection | ±40 V short-circuit proof CAN/LIN pins; ±6 kV HBM/IEC 61000-4-2 ESD; ISO 7637-3 transient immunity; loss-of-ground/loss-of-battery proof HVIOs. |
Applications
| Engine Control Module (ECM) | Body Control Module (BCM) |
|---|---|
|
Use Scenario: Real-time engine parameter monitoring and actuator control under wide battery voltage range (6–16 V), including cranking dips. IC Role / Device Role / Timing Role: Central SBC providing regulated 5 V power, CAN FD communication, dual-LIN sensor interfacing, and HVIO-based injector/valve drive control. Use Value: Maintains microcontroller memory during 2 V battery dips via SMPS boost; enables CAN FD fast-phase updates for torque map downloads without bus interruption. |
Use Scenario: Integrated door module managing window lift, mirror fold, and interior lighting with LIN-connected sensors and CAN gateway functionality. IC Role / Device Role / Timing Role: Power manager and communication hub supplying MCU, buffering LIN commands, and relaying status over CAN to central BCM. Use Value: Dual LIN transceivers reduce external IC count; HVIOs directly drive 12 V loads (e.g., window motor) with open-load diagnostics and limp-home fallback. |
| Advanced Driver Assistance Systems (ADAS) Camera ECU | Electric Power Steering (EPS) Control Unit |
|
Use Scenario: Compact camera ECU requiring low quiescent current in vehicle Sleep mode while retaining wake-up capability via CAN/LIN. IC Role / Device Role / Timing Role: Low-power SBC enabling rapid wake-up from Sleep mode (<100 µs), powering image processor, and managing CAN FD video metadata transport. Use Value: Standby current <30 µA with V1 active; Sleep current <5 µA with V1 off; wake-up latency meets ASAM MCD-2 MC timing requirements. |
Use Scenario: Safety-critical EPS unit needing fail-operational behavior during voltage transients or MCU lockup. IC Role / Device Role / Timing Role: Fault-tolerant SBC delivering watchdog supervision, EN-controlled safety shutdown, and LIMP-triggered mechanical fallback (e.g., centering assist). Use Value: LIMP pin asserts defined waveform upon Overload mode entry; EN pin disables torque motor drivers if MCU fails; watchdog timeout configurable from 8 ms to 4 s. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/5V0 | Same HTQFP48 package and pinout; higher-current boost SMPS (supports full MCU operation down to 2 V, not memory-only). | Preferred where sustained MCU execution during deep battery dip is required - e.g., start-stop systems with extended cranking. | Select UJA1132HW/5V0 if boost output current >100 mA is needed; UJA1135HW/5V0 suffices when only memory retention is critical. |
| TLE9471-3ES | Infineon SBC with 5 V/500 mA LDO, CAN FD transceiver, single LIN, no boost SMPS - relies on external buck for sub-5 V operation. | Used in cost-sensitive modules where battery dips are shallow (<6 V) and memory retention is handled externally. | Choose TLE9471-3ES for simpler power architecture and lower BOM cost; UJA1135HW/5V0 adds integrated boost for deeper voltage resilience. |
Compared with UJA1132HW/5V0, the UJA1135HW/5V0 trades boost current capability for optimized memory-retention efficiency and identical footprint; versus TLE9471-3ES, it provides native boost conversion and dual-LIN support at the cost of higher integration complexity.
Availability
UJA1135HW/5V0Y is available at Aetrix Electronics and suitable for Engine Control Modules, Body Control Modules, ADAS camera ECUs, and Electric Power Steering units requiring stable component supply across automotive production lifecycles.
Supply support for UJA1135HW/5V0Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, with deep expertise in secure connectivity, analog/mixed-signal, and power management solutions.
The UJA113x series is part of NXP's automotive System Basis Chip portfolio, designed specifically for next-generation ECU power management, communication, and fail-safe control in harsh vehicle environments.
FAQ
What is the primary function of the boost mode in UJA1135HW/5V0Y?
The boost mode in UJA1135HW/5V0Y is designed exclusively to maintain power to volatile microcontroller memory during battery voltage dips down to 2 V. Unlike the UJA1131/UJA1132 variants, it does not supply sufficient current for full MCU operation - only memory retention. This is confirmed in Section 2.2 of the official datasheet, which states the boost stage has "limited output current capability" and is "suitable for supplying the memory in a microcontroller to prevent information being lost."
Does UJA1135HW/5V0Y support CAN FD partial networking with CAN FD-passive wake-up?
No, UJA1135HW/5V0Y does not support CAN FD partial networking or CAN FD-passive wake-up. Per Table 1 in the datasheet, only UJA113xFD/x variants include "CAN partial networking; CAN FD passive." The UJA1135HW/5V0Y belongs to the non-FD family and implements classic ISO 11898-2:201x CAN with 2 Mbit/s FD data field support but lacks selective wake-up filtering for CAN FD traffic in Sleep mode.
How many LIN transceivers are active in UJA1135HW/5V0Y, and how are they configured?
UJA1135HW/5V0Y integrates two LIN transceivers (LIN1 and LIN2), both compliant with SAE J2602 and LIN 2.x. However, LIN2 is internally connected per datasheet Figure 3 and Table 3 - pin 25 (LIN2) must be left open on the PCB. Only LIN1 (pins 24, 16, 17) is externally accessible and fully functional; LIN2 serves internal routing only and is not user-configurable.
What are the key differences between UJA1135HW/5V0Y and UJA1131HW/5V0?
Both share the same HTQFP48 package, 5 V/500 mA V1 regulator, dual LIN, and CAN FD transceiver. The core difference lies in SMPS boost capability: UJA1131HW/5V0 features high-current boost supporting full MCU operation at ≥2 V battery, while UJA1135HW/5V0Y uses low-current boost for memory retention only. Additionally, UJA1131HW/5V0 includes 8 HVIOs; UJA1135HW/5V0Y has 4 HVIOs (pins 34–37), with HVIO5–HVIO8 marked "n.c."
Can UJA1135HW/5V0Y operate in Sleep mode with zero V1 output, and how is wake-up initiated?
Yes, UJA1135HW/5V0Y fully disables V1 in Sleep mode to achieve ultra-low quiescent current (<5 µA). Wake-up is initiated exclusively via enabled sources: CAN bus activity (dominant/recessive edge detection), LIN wakeup pulses, or transitions on configured HVIO pins. The system controller validates wake-up conditions before exiting Sleep - no V1 restart occurs without a valid event, ensuring deterministic low-power behavior per Section 7.1.1.4.
UJA1135HW/5V0Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 48-TQFP Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Applications:
- -
- Current - Supply:
- 2.8mA
- Voltage - Supply:
- 2V ~ 28V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-HTQFP (10x10)
UJA1135HW/5V0Y FAQ
1.How can I place an order for UJA1135HW/5V0Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1135HW/5V0Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1135HW/5V0Y reliable?
The price and inventory of UJA1135HW/5V0Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1135HW/5V0Y is usually 5 days.
3.What payment methods are accepted for UJA1135HW/5V0Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1135HW/5V0Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1135HW/5V0Y?
UJA1135HW/5V0Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1135HW/5V0Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1135HW/5V0Y?
For technical support, including UJA1135HW/5V0Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1135HW/5V0Y requirements.
6.How does Aetrix verify that UJA1135HW/5V0Y is sourced from the original manufacturer or authorized distributors?
All UJA1135HW/5V0Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1135HW/5V0Y meets industry standards.
7.What is the process for return or replacement of UJA1135HW/5V0Y?
All UJA1135HW/5V0Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1135HW/5V0Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1135HW/5V0Y part is unused and in its original packaging.
Return procedure for UJA1135HW/5V0Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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