Vishay General Semiconductor - Diodes Division VBUS05M2-HT5-G3-08
- Part No.:
- VBUS05M2-HT5-G3-08
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- 3-XDFN Exposed Pad
- Datasheet:
-
VBUS05M2-HT5-G3-08.pdf
- Description:
- TVS DIODE 5.5VWM 27VC DFN1110-3A
- Quantity:
- Payment:

- Shipping:

Inventory:9,568
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Product details
Overview
VBUS05M2-HT5-G3-08 from Vishay Semiconductors is a 2-line, bidirectional and symmetrical (BiSy) ESD protection diode in DFN1110-3A package, rated for ±5.5 V working voltage, <0.45 pF capacitance, <0.05 μA leakage, and ±20 kV IEC 61000-4-2 contact/air discharge immunity - deployed in high-speed USB2.0/USB3.0 data line protection.
For engineers reviewing the VBUS05M2-HT5-G3-08 datasheet, VBUS05M2-HT5-G3-08 pinout, VBUS05M2-HT5-G3-08 application, or VBUS05M2-HT5-G3-08 equivalent, key selection criteria include low clamping voltage (11–18 V at 1–3.4 A), dynamic resistance ≤1 Ω, AEC-Q101 qualification, and DFN1110-3A footprint compatibility with high-density PCB layouts.
Technical Context
The VBUS05M2-HT5-G3-08 implements a three-terminal BiSy architecture with two identical protection paths (Pin 1→Pin 3 and Pin 2→Pin 3), each featuring a Zener diode for precise breakdown control and dual low-capacitance switching diodes for fast transient response. Its symmetrical clamping ensures equal positive/negative transient suppression without polarity dependency.
Designed for signal integrity-critical interfaces, it delivers <0.45 pF load capacitance at 0–3.3 V bias and maintains stable clamping performance up to 150 °C junction temperature, supporting automotive-grade reliability per AEC-Q101 with MSL Level 1 soldering compatibility (peak 260 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Protection Lines | 2 independent bidirectional channels (Pin 1 & Pin 2 to Pin 3) |
| Working Voltage | ±5.5 V max reverse stand-off - supports USB2.0/3.0 and HDMI DC bias rails |
| Clamping Voltage | 11–13 V at 1 A IPP; 15–18 V at 3.4 A IPP - limits downstream IC stress during ESD events |
| Capacitance | 0.37–0.45 pF at 1 MHz and 0/3.3 V - preserves signal integrity up to 5 Gbps |
| ESD Rating | ±20 kV contact & air discharge (IEC 61000-4-2) - exceeds industrial and automotive immunity requirements |
| Leakage Current | <0.001 μA typical at 5.5 V - avoids signal distortion or power loss in always-on lines |
| Dynamic Resistance | ≤1 Ω (TLP, 100 ns) - enables rapid energy diversion with minimal voltage overshoot |
Pinout & Package
VBUS05M2-HT5-G3-08 is housed in a 3-pin DFN1110-3A package (1.1 × 1.0 × 0.4 mm), with exposed thermal pad (non-electrical), e3 tin-plated terminations, and AOI-compatible marking. Pin 1 and Pin 2 serve as protected I/O terminals; Pin 3 is common cathode/anode ground reference.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Protected Data Line 1 Input/Output | Bidirectional ESD path to Pin 3; connects to USB D+ or HDMI TMDS+ |
| Pin 2 | Protected Data Line 2 Input/Output | Bidirectional ESD path to Pin 3; connects to USB D− or HDMI TMDS− |
| Pin 3 | Common Ground Reference | Shared cathode/anode node for both protection paths; must connect to low-impedance system ground |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional & Symmetrical (BiSy) Clamping | Equal ±7.5–9.5 V breakdown and ±11–18 V clamping across both polarities - eliminates need for polarity-aware layout |
| Ultra-Low Capacitance | 0.37 pF typical at 0 V bias - minimizes insertion loss and reflection in 480 Mbps–5 Gbps differential links |
| AEC-Q101 Qualified | Qualified per human body model Class H3B (>8 kV) and full automotive temperature range (−55 to +150 °C) |
| DFN1110-3A Footprint | 1.1 × 1.0 mm body with 0.65 mm pitch - enables routing under fine-pitch connectors and dense USB/HDMI interfaces |
| e3 Tin Plating & MSL Level 1 | Tin-plated side walls and moisture sensitivity level 1 - supports standard reflow without baking or special handling |
Applications
| USB 2.0 High-Speed Interface | HDMI 1.4 Differential Signaling |
|---|---|
Use Scenario: Protecting D+ and D− lines of USB 2.0 transceivers against ESD events during hot-plug or cable handling in portable devices. IC Role / Device Role / Timing Role: Two-channel bidirectional ESD clamp placed immediately before the PHY, referenced to clean system ground. Use Value: 0.45 pF capacitance prevents signal rise-time degradation; ±20 kV immunity meets IEC 61000-4-2 compliance for end-user accessibility. | Use Scenario: Safeguarding TMDS+ and TMDS− pairs in HDMI 1.4 source/sink ports against electrostatic discharge in consumer AV equipment. IC Role / Device Role / Timing Role: Symmetrical clamping device on each differential pair, with shared ground return to minimize common-mode noise coupling. Use Value: ≤1 Ω dynamic resistance ensures sub-nanosecond response; clamping below 18 V protects 3.3 V tolerant HDMI receivers. |
| Automotive Infotainment USB Port | Industrial USB-C Docking Station |
Use Scenario: ESD hardening of front-panel USB ports in automotive head units exposed to dry-climate static discharge. IC Role / Device Role / Timing Role: AEC-Q101-qualified protection element mounted at connector entry point, with thermal pad tied to internal ground plane. Use Value: −55 to +150 °C operation supports under-hood ambient extremes; ±5.5 V working range matches USB VBUS tolerance margins. | Use Scenario: Dual-lane ESD protection for USB-C SuperSpeed lanes in multi-port docking stations with frequent cable insertion cycles. IC Role / Device Role / Timing Role: Compact 2-channel solution minimizing board area while maintaining independent clamping for each high-speed differential pair. Use Value: DFN1110-3A footprint allows placement adjacent to USB-C receptacle; low leakage avoids phantom charging issues in standby mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | Single-channel, 0.5 pF typical capacitance, ±12 kV IEC 61000-4-2, no AEC-Q101 rating | Requires two devices for dual-line protection; not qualified for automotive environments | Select when cost-sensitive consumer designs prioritize footprint over automotive qualification and ultra-low capacitance |
| SZ1.8SMAT5G | Unidirectional, 1.8 V standoff, 12 pF capacitance, ±30 kV ESD rating, TO-236 package | Not suitable for high-speed data lines due to high capacitance; requires polarity-aware routing | Choose only for low-frequency power rail or GPIO protection where speed and symmetry are irrelevant |
Compared with TPD2E001DRYR and SZ1.8SMAT5G, the VBUS05M2-HT5-G3-08 uniquely combines dual-channel symmetry, sub-0.45 pF capacitance, AEC-Q101 qualification, and DFN1110-3A packaging - making it the only option that satisfies simultaneous requirements for USB3.0 signal integrity, automotive reliability, and space-constrained layouts.
Availability
VBUS05M2-HT5-G3-08 is available at Aetrix Electronics and suitable for USB2.0/3.0 interface protection, HDMI 1.4 differential line safeguarding, and automotive infotainment port hardening requiring stable component supply and long-term lifecycle support.
Supply support for VBUS05M2-HT5-G3-08 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in high-reliability diodes, MOSFETs, optoelectronics, and protection devices with emphasis on automotive, industrial, and computing applications.
The VBUS05M2-HT5-G3-08 belongs to Vishay's BiSy ESD protection family, engineered specifically for high-speed serial interfaces where low capacitance, symmetrical clamping, and AEC-Q101 compliance are mandatory design constraints.
FAQ
What is the maximum operating temperature range for the VBUS05M2-HT5-G3-08?
The VBUS05M2-HT5-G3-08 supports a junction temperature range of −55 °C to +150 °C, fully compliant with AEC-Q101 requirements for automotive under-hood and infotainment applications. This extended range ensures reliable operation in harsh thermal environments without derating, and its MSL Level 1 rating permits standard reflow soldering without pre-baking.
Does the VBUS05M2-HT5-G3-08 require external biasing or control signals?
No, the VBUS05M2-HT5-G3-08 is a passive, unidirectional/bidirectional Zener-based ESD clamp with no external bias or enable pins. It operates automatically across its ±5.5 V working range, drawing less than 0.001 μA leakage at rated voltage. The device relies solely on its internal BiSy structure - Pin 1 and Pin 2 clamp symmetrically to Pin 3 ground without any active circuitry or configuration.
How does the VBUS05M2-HT5-G3-08 achieve 0.37 pF capacitance while maintaining ±20 kV ESD immunity?
The VBUS05M2-HT5-G3-08 achieves ultra-low capacitance through a hybrid structure: each protection path integrates a precision Zener diode for controlled breakdown voltage (7.5–9.5 V) and two low-capacitance switching diodes optimized for minimal junction area. This architecture separates clamping function from capacitance generation, enabling <0.45 pF at 1 MHz while sustaining ±20 kV IEC 61000-4-2 immunity via robust silicon design and optimized doping profiles.
Can the VBUS05M2-HT5-G3-08 be used to protect a single-ended signal like a UART line?
Yes, the VBUS05M2-HT5-G3-08 can protect a single-ended signal by using one channel (e.g., Pin 1 to Pin 3) while leaving Pin 2 unconnected or grounded, though this underutilizes its dual-channel capability. Its ±5.5 V working range suits 3.3 V or 5 V UART rails, and its <0.05 μA leakage avoids loading. However, for dedicated single-ended protection, smaller-footprint single-channel alternatives may offer better cost-per-channel efficiency.
Is the thermal pad on the VBUS05M2-HT5-G3-08 electrically connected or isolated?
The exposed thermal pad on the VBUS05M2-HT5-G3-08 is electrically isolated from all internal circuitry and serves only for mechanical attachment and thermal conduction. Vishay's package documentation specifies no electrical connection between the pad and any pin; it may be left floating or tied to ground for improved thermal performance, but grounding does not affect ESD clamping behavior or electrical characteristics of the VBUS05M2-HT5-G3-08.
VBUS05M2-HT5-G3-08 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- 3-XDFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 2
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 7.5V
- Voltage - Clamping (Max) @ Ipp:
- 27V (Typ)
- Current - Peak Pulse (10/1000µs):
- 3.4A (8/20µs)
- Power - Peak Pulse:
- 60W
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 0.37pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- DFN1110-3A
VBUS05M2-HT5-G3-08 FAQ
1.How can I place an order for VBUS05M2-HT5-G3-08 through Aetrix?
Please submit a Request for Quotation (RFQ) for VBUS05M2-HT5-G3-08 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for VBUS05M2-HT5-G3-08 reliable?
The price and inventory of VBUS05M2-HT5-G3-08 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for VBUS05M2-HT5-G3-08 is usually 5 days.
3.What payment methods are accepted for VBUS05M2-HT5-G3-08?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for VBUS05M2-HT5-G3-08 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for VBUS05M2-HT5-G3-08?
VBUS05M2-HT5-G3-08 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your VBUS05M2-HT5-G3-08 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for VBUS05M2-HT5-G3-08?
For technical support, including VBUS05M2-HT5-G3-08 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your VBUS05M2-HT5-G3-08 requirements.
6.How does Aetrix verify that VBUS05M2-HT5-G3-08 is sourced from the original manufacturer or authorized distributors?
All VBUS05M2-HT5-G3-08 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that VBUS05M2-HT5-G3-08 meets industry standards.
7.What is the process for return or replacement of VBUS05M2-HT5-G3-08?
All VBUS05M2-HT5-G3-08 units undergo pre-shipment inspection (PSI). If there is an issue with VBUS05M2-HT5-G3-08, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The VBUS05M2-HT5-G3-08 part is unused and in its original packaging.
Return procedure for VBUS05M2-HT5-G3-08:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
VBUS05M2-HT5-G3-08 Tags

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Diodes Incorporated

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Toshiba Semiconductor and Storage

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Diodes Incorporated
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