Vishay General Semiconductor - Diodes Division VGSOT12C-G3-08
- Part No.:
- VGSOT12C-G3-08
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Category:
- TVS Diodes
- Package:
- TO-236-3, SC-59, SOT-23-3
- Datasheet:
-
VGSOT12C-G3-08.pdf
- Description:
- TVS DIODE 12VWM 26VC SOT23-3
- Quantity:
- Payment:

- Shipping:

Inventory:5,618
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Product details
Overview
VGSOT12C-G3-08 from Vishay Semiconductors is a two-line unidirectional ESD protection diode in SOT-23 package, featuring common-anode dual-channel configuration, 12 V maximum reverse working voltage (VRWM), ±30 kV IEC 61000-4-2/ISO 10605 ESD immunity, and 480 W peak pulse power (8/20 μs). It protects high-speed data lines such as USB 2.0 and HDMI interfaces against electrostatic discharge.
For engineers reviewing the VGSOT12C-G3-08 datasheet, VGSOT12C-G3-08 pinout, VGSOT12C-G3-08 application, or VGSOT12C-G3-08 equivalent, key selection criteria include VRWM = 12 V, clamping voltage ≤26 V at 18.5 A (8/20 μs), 115–150 pF capacitance at 0 V bias, AEC-Q101 qualification, and SOT-23 footprint compatibility with space-constrained PCB layouts.
Technical Context
The VGSOT12C-G3-08 implements BiAs-MODE (Bidirectional Asymmetrical) protection when pins 1 and 2 connect to signal lines and pin 3 to ground - enabling independent forward/reverse clamping: low VF (~2.5 V at 18.5 A) for negative transients and VBR-based reverse clamping (~20.2–26 V at 18.5 A). Its dual-diode common-anode topology supports two-line protection without shared cathodes.
In BiSy-MODE (single-line bidirectional symmetrical), pins 1 and 2 form a series-connected pair with pin 3 left floating, delivering matched ±16.4–19.7 V clamping at 1 A and 23.4–28.1 V at 18.5 A, leveraging identical VBR and VF characteristics across both polarities for balanced transient suppression.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VRWM | 12 V - defines maximum continuous operating voltage before leakage exceeds 1 μA; sets safe margin for 12 V nominal bus systems. |
| VBR (min/typ/max) | 13.5 / 15 / 16.5 V at 1 mA - determines onset of reverse conduction; ensures robust turn-on above system operating voltage. |
| VC (at 18.5 A, 8/20 μs) | 20.2–26 V - peak clamped voltage during worst-case surge; directly limits stress on downstream ICs like USB PHYs. |
| Capacitance (0 V, 1 MHz) | 115–150 pF - impacts signal integrity on high-speed lines; suitable for ≤480 Mbps USB 2.0 but not USB 3.0. |
| IPP (8/20 μs) | 18.5 A - maximum single-shot surge current it can divert without failure; enables compliance with IEC 61000-4-5 Level 3. |
| ESD immunity | ±30 kV contact/air per IEC 61000-4-2 & ISO 10605 - exceeds industrial and automotive ESD requirements for user-accessible ports. |
| AEC-Q101 qualified | Yes - validated for automotive under-hood and infotainment applications requiring HBM >8 kV and temperature cycling reliability. |
Pinout & Package
SOT-23 package (JEDEC TO-236AB), 3-pin, e3 Sn-plated terminations, MSL level 1, 9.2 mg weight, UL 94 V-0 molding compound.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Anode of Diode 1 | Connects to first protected signal line (L1); forms one half of dual-channel ESD path to ground via Pin 3. |
| Pin 2 | Anode of Diode 2 | Connects to second protected signal line (L2); shares common cathode (Pin 3) with Diode 1 for compact layout. |
| Pin 3 | Common Cathode | Must be connected to system ground; carries combined surge current from both diodes during BiAs operation. |
Key Features
| Feature | Design Value |
|---|---|
| Two-line unidirectional protection | Dual-channel common-anode architecture protects two independent data lines (e.g., D+ and D−) with single device, reducing BOM count and board area. |
| Bidirectional asymmetrical (BiAs) clamping | Clamps negative transients near ground (VF ≈ 2.5 V @ 18.5 A) and positive transients at higher voltage (VC ≈ 20–26 V), optimizing protection for asymmetric signal swings. |
| Configurable as bidirectional single-line (BiSy) | By leaving Pin 3 unconnected and using Pins 1–2, achieves symmetrical ±23–28 V clamping for legacy RS-485 or CAN bus protection without redesign. |
| AEC-Q101 qualified | Validated for automotive environments including temperature cycling, humidity, and mechanical shock - supports Tier-1 supplier compliance requirements. |
| Low leakage at VRWM | IR ≤ 1 μA at 12 V reverse bias minimizes standby power loss and avoids false triggering in battery-powered sensor nodes. |
Applications
| USB 2.0 Interface Protection | HDMI Data Lane Protection |
|---|---|
Use Scenario: Protecting D+ and D− differential pairs in portable USB host/device ports exposed to user-handling ESD events. IC Role / Device Role: Primary ESD clamp placed immediately before USB transceiver IC, shunting transients to chassis ground. Use Value: 12 V VRWM matches USB 2.0 signaling range; 115–150 pF capacitance preserves signal integrity up to 480 Mbps without eye diagram degradation. |
Use Scenario: Safeguarding TMDS clock and data channels in consumer HDMI sources (e.g., set-top boxes) against contact discharge. IC Role / Device Role: Point-of-entry protection on HDMI connector side, preceding EMI filter and receiver IC. Use Value: ±30 kV ESD rating exceeds IEC 61000-4-2 Level 4; low 115–150 pF capacitance prevents skew between differential pairs. |
| Automotive Infotainment Serial Links | Industrial RS-485 Transceiver Protection |
Use Scenario: Securing LVDS or FPD-Link II video/data buses in automotive head units subjected to harsh ESD environments. IC Role / Device Role: Dual-line clamp on high-speed serial links between display module and main processor. Use Value: AEC-Q101 qualification ensures reliability across -40 °C to +125 °C junction temperatures; 480 W peak power handles load-dump-induced surges. |
Use Scenario: Adding robust ESD resilience to RS-485 transceivers in factory automation PLCs with frequent cable hot-plug events. IC Role / Device Role: BiSy-mode configuration (Pins 1–2 only) provides symmetrical ±23–28 V clamping on A/B differential lines. Use Value: Eliminates need for separate bidirectional TVS; 12.5 V VRWM aligns with RS-485 common-mode range while maintaining noise margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMAJ12A | Single-line unidirectional TVS; 12 V VRWM, 300 W PPPM (8/20 μs), 15.6 V VC @ 12.3 A; SMC package (larger than SOT-23). | Requires two devices for dual-line protection; lacks integrated common-cathode topology and BiSy mode flexibility. | Select when higher surge rating is needed and board space allows larger SMC footprint; not drop-in for dual-line routing. |
| TPD2E001DRSR | Two-line unidirectional ESD array; 5 V VRWM, 0.8 pF typical capacitance, ±15 kV ESD rating; same SOT-23-3 package. | Lower VRWM and ESD rating; optimized for ultra-high-speed interfaces (e.g., USB 3.0, MIPI), not 12 V systems. | Choose for sub-5 V logic-level data lines where ultra-low capacitance is critical; unsuitable for 12 V bus protection. |
Compared with SMAJ12A and TPD2E001DRSR, VGSOT12C-G3-08 uniquely delivers dual-line 12 V protection in SOT-23 with ±30 kV ESD immunity and field-configurable BiAs/BiSy modes - making it optimal for space-constrained automotive and industrial data interfaces where voltage rating, surge capability, and layout efficiency are jointly critical.
Availability
VGSOT12C-G3-08 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI data lane hardening, and automotive infotainment serial link safeguarding requiring stable component supply across production lifecycles.
Supply support for VGSOT12C-G3-08 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Semiconductors is a global leader in discrete semiconductors, specializing in high-reliability diodes, MOSFETs, optoelectronics, and passive components for automotive, industrial, and computing markets.
The VGSOTxxC family is engineered specifically for high-density ESD protection of high-speed data lines, balancing low capacitance, precise VRWM matching, and AEC-Q101 qualification for demanding automotive and industrial applications.
FAQ
What is the maximum reverse working voltage (VRWM) of the VGSOT12C-G3-08?
The VGSOT12C-G3-08 has a maximum reverse working voltage (VRWM) of 12 V, verified per electrical characteristics table on page 7 of Vishay document 86325. This value defines the highest continuous DC or peak AC voltage the device blocks before leakage exceeds 1 μA, making it suitable for 12 V nominal bus systems such as automotive infotainment data links and industrial control interfaces.
Does the VGSOT12C-G3-08 support bidirectional ESD protection?
Yes, the VGSOT12C-G3-08 supports two distinct bidirectional modes: BiAs-MODE (pins 1 & 2 to signal lines, pin 3 to ground) delivers asymmetrical clamping - low VF for negative transients and VBR-based clamping for positive ones - and BiSy-MODE (pins 1 & 2 used as a pair, pin 3 unconnected) provides symmetrical ±23–28 V clamping ideal for RS-485 or CAN bus protection.
Is the VGSOT12C-G3-08 qualified to AEC-Q101 standards?
Yes, the VGSOT12C-G3-08 is explicitly AEC-Q101 qualified as confirmed in the "FEATURES" section (page 1) and "PACKAGE DATA" table (page 2) of Vishay document 86325. This qualification covers stress tests including temperature cycling, high-temperature operating life, and ESD robustness, validating its use in automotive under-hood and cabin electronics.
What is the clamping voltage of the VGSOT12C-G3-08 under a full-rated surge?
Under an 18.5 A, 8/20 μs surge (IPPM), the VGSOT12C-G3-08 clamps to 20.2–26 V as specified in the "ELECTRICAL CHARACTERISTICS" table for VGSOT12C (page 7). This clamping voltage is measured across the protected line and ground, and directly determines the maximum overvoltage imposed on downstream ICs such as USB transceivers or HDMI receivers.
Can the VGSOT12C-G3-08 be used for USB 2.0 data line protection?
Yes, the VGSOT12C-G3-08 is well-suited for USB 2.0 D+/D− line protection: its 12 V VRWM accommodates USB's 3.3 V nominal signaling with ample margin, 115–150 pF capacitance preserves signal integrity up to 480 Mbps, and ±30 kV ESD rating exceeds IEC 61000-4-2 Level 4 - all confirmed in Vishay document 86325 sections 1, 7, and 9.
VGSOT12C-G3-08 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay General Semiconductor - Diodes Division
- Package/Case:
- TO-236-3, SC-59, SOT-23-3
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 12V (Max)
- Voltage - Breakdown (Min):
- 13.5V
- Voltage - Clamping (Max) @ Ipp:
- 26V
- Current - Peak Pulse (10/1000µs):
- 18.5A (8/20µs)
- Power - Peak Pulse:
- 480W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 115pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-3
VGSOT12C-G3-08 FAQ
1.How can I place an order for VGSOT12C-G3-08 through Aetrix?
Please submit a Request for Quotation (RFQ) for VGSOT12C-G3-08 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for VGSOT12C-G3-08 reliable?
The price and inventory of VGSOT12C-G3-08 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for VGSOT12C-G3-08 is usually 5 days.
3.What payment methods are accepted for VGSOT12C-G3-08?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for VGSOT12C-G3-08 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for VGSOT12C-G3-08?
VGSOT12C-G3-08 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your VGSOT12C-G3-08 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for VGSOT12C-G3-08?
For technical support, including VGSOT12C-G3-08 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your VGSOT12C-G3-08 requirements.
6.How does Aetrix verify that VGSOT12C-G3-08 is sourced from the original manufacturer or authorized distributors?
All VGSOT12C-G3-08 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that VGSOT12C-G3-08 meets industry standards.
7.What is the process for return or replacement of VGSOT12C-G3-08?
All VGSOT12C-G3-08 units undergo pre-shipment inspection (PSI). If there is an issue with VGSOT12C-G3-08, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The VGSOT12C-G3-08 part is unused and in its original packaging.
Return procedure for VGSOT12C-G3-08:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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