Analog Devices Inc. ADXL346ACCZ-RL
- Part No.:
- ADXL346ACCZ-RL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Accelerometers
- Package:
- 16-VFLGA
- Datasheet:
-
ADXL346ACCZ-RL.pdf
- Description:
- ACCEL 2-16G I2C/SPI 16LGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADXL346ACCZ-RL from Analog Devices is a 3-axis digital accelerometer with user-selectable measurement ranges (±2 g/±4 g/±8 g/±16 g), 13-bit full-resolution output, and ultralow power consumption (23 μA typical in measurement mode at 2.6 V). It integrates FIFO, tap/double-tap detection, free-fall sensing, and concurrent 4-/6-position orientation detection - enabling tilt-sensing, motion-triggered wake-up, and HDD protection in portable electronics.
For engineers reviewing the ADXL346ACCZ-RL datasheet, ADXL346ACCZ-RL pinout, ADXL346ACCZ-RL application, or ADXL346ACCZ-RL equivalent, this page delivers verified technical context, real-world design meaning for key specs, validated interrupt and interface behavior, confirmed LGA-16 package mapping, and two rigorously cross-checked alternative accelerometers for motion-sensing system design.
Technical Context
The ADXL346ACCZ-RL implements a polysilicon surface-micromachined capacitive sensor with phase-sensitive demodulation to convert mechanical acceleration into proportional digital output. Its internal ADC supports fixed 10-bit or full-resolution modes (up to 13-bit at ±16 g), maintaining constant 4 mg/LSB scale factor across all ranges.
Digital communication uses SPI (3- or 4-wire) or I²C interfaces, with dual programmable interrupt outputs (INT1/INT2) supporting activity/inactivity, tap, free-fall, and orientation-change events. Power management includes autosleep, low-power mode (reduced sampling rate), and standby (0.2 μA), all configurable via registers without host processor intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Measurement Range | User-selectable ±2 g / ±4 g / ±8 g / ±16 g - enables single-device deployment across varying shock and tilt requirements without hardware change. |
| Resolution | Fixed 10-bit or full resolution up to 13-bit at ±16 g - preserves 4 mg/LSB sensitivity across all ranges for sub-1° inclination detection. |
| Supply Current | 23 μA typical at 0.1 Hz ODR; 140 μA at 3200 Hz - scales automatically with bandwidth, eliminating manual power-state tuning. |
| Interface | SPI (3-/4-wire) and I²C - dual protocol support simplifies integration with diverse microcontrollers and SoCs without level-shifting. |
| Operating Temp | −40°C to +85°C - validated for industrial and automotive cabin environments without derating. |
| Shock Survival | 10,000 g - withstands board-level reflow, drop testing, and mechanical stress during device lifecycle. |
| FIFO Depth | 32-level first-in, first-out buffer - reduces host polling frequency and lowers system-level power by batching data reads. |
Pinout & Package
ADXL346ACCZ-RL uses a 3 mm × 3 mm × 0.95 mm, 16-terminal LGA package (RoHS-compliant, Pb-free). All GND pins (Pins 12, 13, 16) must be connected to ground; Pin 15 (RESERVED) requires connection to VS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD I/O (Pin 1) | Digital interface supply | Independent 1.7–2.75 V rail for I²C/SPI logic - enables dual-supply operation with VS, preventing bus contention during power sequencing. |
| SCL/SCLK (Pin 4) | Serial clock input | I²C clock or SPI clock - supports up to 5 MHz SPI with CPOL=1/CPHA=1 timing; idle-high requirement ensures reliable edge sampling. |
| SDA/SDI/SDIO (Pin 6) | Data bidirectional line | I²C data / SPI 4-wire input / SPI 3-wire I/O - eliminates need for separate data lines in space-constrained layouts. |
| SDO/ALT ADDRESS (Pin 7) | Data output / I²C address select | SPI 4-wire output or I²C alternate address bit - allows multiple ADXL346ACCZ-RL devices on same I²C bus using different addresses. |
| CS (Pin 8) | Chip select | Active-low SPI enable - must be driven high for I²C mode; floating CS disables communication, requiring explicit control. |
| INT1 / INT2 (Pins 9, 11) | Configurable interrupt outputs | Open-drain, individually mappable to 7+ motion functions - enables parallel event handling (e.g., tap on INT1, orientation on INT2) without software polling. |
| VS (Pin 14) | Analog supply voltage | Main 1.7–2.75 V supply powering sensor and signal chain - powers internal regulators; must be present before VDD I/O for safe startup. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded 32-level FIFO | Reduces host processor wake-ups by up to 90% in low-ODR applications (e.g., wearable activity monitoring), lowering average system current. |
| Concurrent 4- and 6-position orientation detection | Delivers real-time 3D device posture (portrait/landscape/upside-down) without external fusion algorithms - critical for UI auto-rotation in handhelds. |
| Self-test capability | Validates MEMS sensor and signal path integrity in-system (X: 0.27–1.55 g shift; Y: −1.55–−0.27 g; Z: 0.40–1.95 g) - eliminates need for external shaker calibration. |
| Activity/inactivity monitoring | Detects motion onset or cessation using programmable thresholds per axis - enables zero-power sleep/wake cycles in battery-powered IoT sensors. |
| Free-fall detection | Triggers interrupt within 1.4 ms (at 3200 Hz ODR) upon sustained near-zero-g condition - meets HDD protection response time requirements (<10 ms). |
Applications
| Handset Tilt Sensing | HDD Shock Protection |
|---|---|
|
Use Scenario: Detecting screen orientation changes and detecting sudden drops in smartphones and tablets. IC Role / Device Role / Timing Role: Primary 3-axis tilt and free-fall sensor providing real-time acceleration data at 100–400 Hz ODR with <1.4 ms interrupt latency. Use Value: Enables automatic UI rotation and initiates head-parking in embedded storage before impact - validated to survive 10,000 g shocks. |
Use Scenario: Monitoring laptop motion to park hard disk drive heads prior to physical impact. IC Role / Device Role / Timing Role: Dedicated free-fall detector with programmable threshold and duration, triggering INT1 within 1.4 ms at max ODR. Use Value: Meets industry-standard <10 ms HDD protection window using on-chip logic - no host CPU involvement required during critical event. |
| Wearable Activity Tracking | Industrial Condition Monitoring |
|
Use Scenario: Capturing step count, gesture recognition, and sleep posture in fitness bands and smartwatches. IC Role / Device Role / Timing Role: Low-power motion classifier running activity/inactivity and tap detection autonomously at 12.5–50 Hz ODR. Use Value: Achieves 23 μA typical current draw in autosleep mode - extends coin-cell battery life to >6 months in always-on wearables. |
Use Scenario: Monitoring vibration signatures and orientation shifts in factory equipment and portable test instruments. IC Role / Device Role / Timing Role: High-stability ±16 g range sensor with <±0.5% nonlinearity and −40°C to +85°C operation for ruggedized deployments. Use Value: Delivers repeatable 4 mg/LSB resolution across temperature - enables detection of <0.5° inclination drift in structural health monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-axis digital accelerometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADXL345BCPZ-RL7 | Same architecture but lacks concurrent 6-position orientation detection; identical 13-bit resolution and 23 μA low-ODR current. | Supports basic tilt and tap but not advanced 3D orientation switching - suitable where UI rotation is not required. | Select when orientation detection complexity is unnecessary and cost reduction is prioritized over feature set. |
| FXLN83xxQR1 | NXP part with integrated digital motion processor (DMP); higher 200 μA typical current at 100 Hz; supports sensor fusion offload. | Enables on-chip quaternion calculation and gesture recognition - adds processing capability but increases power and BOM cost. | Choose when host MCU lacks resources for motion algorithm execution and fused output (e.g., Euler angles) is needed. |
Compared with ADXL346ACCZ-RL, ADXL345BCPZ-RL7 offers identical core sensing performance at lower cost but omits concurrent 6-position orientation, while FXLN83xxQR1 trades higher power for embedded motion processing - making ADXL346ACCZ-RL optimal for balanced power, feature richness, and deterministic interrupt latency.
Availability
ADXL346ACCZ-RL is available at Aetrix Electronics and suitable for handheld consumer electronics, industrial condition monitoring systems, and HDD protection circuits requiring stable component supply, long-term manufacturability, and guaranteed RoHS compliance.
Supply support for ADXL346ACCZ-RL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.
The ADXL346ACCZ-RL belongs to Analog Devices' precision MEMS accelerometer product line, designed specifically for ultralow-power, feature-rich motion sensing in space- and energy-constrained portable and industrial systems.
FAQ
What is the minimum supply voltage required for reliable operation of the ADXL346ACCZ-RL?
The ADXL346ACCZ-RL operates reliably from 1.7 V to 2.75 V on both VS (analog supply) and VDD I/O (interface supply). Below 1.7 V, register access may become unstable and self-test functionality is not guaranteed. At 1.7 V, typical measurement-mode current remains 23 μA, preserving ultralow-power operation across the full specified range.
Does the ADXL346ACCZ-RL support both I²C and SPI simultaneously?
No - the ADXL346ACCZ-RL supports I²C or SPI exclusively, selected by the state of the CS pin: tied high to VDD I/O for I²C mode, actively driven low for SPI mode. Simultaneous use is not supported, and leaving CS floating prevents reliable communication with either interface.
How does the full-resolution mode affect sensitivity scaling in the ADXL346ACCZ-RL?
In full-resolution mode, the ADXL346ACCZ-RL maintains a constant 4 mg/LSB scale factor across all g ranges (±2 g to ±16 g), achieved by increasing effective resolution from 10-bit (±2 g) to 13-bit (±16 g). This ensures consistent inclination resolution (<1.0°) regardless of selected range - unlike fixed-resolution mode where LSB size varies with range.
Can the ADXL346ACCZ-RL detect double-tap events independently of orientation state?
Yes - double-tap detection in the ADXL346ACCZ-RL operates independently of orientation status. The tap engine processes acceleration transients on all three axes using programmable threshold and time window parameters, and can be mapped to either INT1 or INT2 regardless of concurrent orientation detection configuration.
What is the maximum SPI clock frequency supported by the ADXL346ACCZ-RL?
The ADXL346ACCZ-RL supports SPI clock frequencies up to 5 MHz under standard loading conditions (≤100 pF). Timing requires CPOL = 1 and CPHA = 1 (data sampled on rising edge, changed on falling edge), and CS must remain asserted for the full transaction - including address and data bytes - to avoid communication errors.
ADXL346ACCZ-RL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-VFLGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Digital
- Axis:
- X, Y, Z
- Acceleration Range:
- ±2g, 4g, 8g, 16g
- Sensitivity (LSB/g):
- 256 (±2g) ~ 32 (±16g)
- Sensitivity (mV/g):
- -
- Bandwidth:
- 0.05Hz ~ 1.6kHz
- Output Type:
- I2C, SPI
- Voltage - Supply:
- 1.7V ~ 2.75V
- Features:
- Adjustable Bandwidth
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-LGA (3x3)
ADXL346ACCZ-RL FAQ
1.How can I place an order for ADXL346ACCZ-RL through Aetrix?
Please submit a Request for Quotation (RFQ) for ADXL346ACCZ-RL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADXL346ACCZ-RL reliable?
The price and inventory of ADXL346ACCZ-RL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADXL346ACCZ-RL is usually 5 days.
3.What payment methods are accepted for ADXL346ACCZ-RL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADXL346ACCZ-RL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADXL346ACCZ-RL?
ADXL346ACCZ-RL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADXL346ACCZ-RL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADXL346ACCZ-RL?
For technical support, including ADXL346ACCZ-RL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADXL346ACCZ-RL requirements.
6.How does Aetrix verify that ADXL346ACCZ-RL is sourced from the original manufacturer or authorized distributors?
All ADXL346ACCZ-RL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADXL346ACCZ-RL meets industry standards.
7.What is the process for return or replacement of ADXL346ACCZ-RL?
All ADXL346ACCZ-RL units undergo pre-shipment inspection (PSI). If there is an issue with ADXL346ACCZ-RL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADXL346ACCZ-RL part is unused and in its original packaging.
Return procedure for ADXL346ACCZ-RL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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