Alpha & Omega Semiconductor Inc. AOZ8001AJI-05
- Part No.:
- AOZ8001AJI-05
- Manufacturer:
- Alpha & Omega Semiconductor Inc.
- Category:
- TVS Diodes
- Package:
- TO-253-4, TO-253AA
- Datasheet:
-
AOZ8001AJI-05.pdf
- Description:
- TVS DIODE 5VWM 16VC SOT143-4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AOZ8001AJI-05 from Alpha & Omega Semiconductor is an ultra-low capacitance TVS diode array designed to protect two high-speed data lines (e.g., USB D+/D−) against ESD and lightning surges. It features 1.8 pF I/O-to-GND capacitance, ±30 kV IEC 61000-4-2 contact/air discharge rating, 5.5 V working peak reverse voltage (VRWM), 12.5 V max clamping voltage at 1 A IPP, and operates from −40°C to +85°C in SOT-143 package.
For engineers reviewing the AOZ8001AJI-05 datasheet, pinout, applications, or equivalent options, key selection criteria include low-capacitance signal integrity preservation, IEC 61000-4-2 Level 4 compliance, dual-line protection architecture, and compatibility with 5 V interface systems such as USB 2.0 and DVI.
Technical Context
The AOZ8001AJI-05 integrates four surge-rated steering diodes and one bidirectional TVS in a single SOT-143 package. Its internal topology routes transients from either I/O line (CH1 or CH2) to VP (pin 4, positive supply rail) or VN (pin 1, ground reference), enabling bidirectional clamping without external bias components when VP is connected to +5 V.
It delivers 18 A surge current handling per IEC 61000-4-5 (8/20 µs), maintains ≤1.8 pF capacitance at 0 V bias (f = 1 MHz), and achieves <12.5 V clamping at 1 A IPP - critical for preserving signal fidelity on 480 Mbps USB 2.0 differential pairs while meeting industrial ESD immunity requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VRWM | 5.5 V - ensures reliable operation on 5 V data/power rails without leakage or false triggering |
| VBR (min) | 8.5 V @ 1 mA - guarantees breakdown only during overvoltage events, not during normal 5 V signaling |
| VCL (max) @ 1 A | 12.5 V - limits transient voltage seen by downstream ICs to safe levels during ESD strikes |
| CJ (typ) | 1.8 pF @ VR = 0 V, 1 MHz - preserves signal integrity on high-speed interfaces up to 480 Mbps |
| ESD Rating | ±30 kV air/contact per IEC 61000-4-2 Level 4 - exceeds standard system-level ESD immunity requirements |
| Surge Rating | 18 A (8/20 µs) per IEC 61000-4-5 - withstands lightning-induced surges on exposed I/O lines |
| Operating Temp | −40°C to +85°C ambient - supports deployment in industrial and consumer equipment environments |
Pinout & Package
SOT-143 (4-pin, 1.92 mm × 1.37 mm × 0.95 mm) surface-mount package with RoHS-compliant, lead-free finish; optimized for minimal PCB footprint and low parasitic inductance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VN) | Ground Reference Terminal | Common cathode connection for steering diodes; must be tied directly to low-impedance system ground |
| 2 (CH1) | Data Line 1 Input/Output | Protects first high-speed signal line (e.g., USB D+); bidirectionally clamps to VN or VP |
| 3 (CH2) | Data Line 2 Input/Output | Protects second high-speed signal line (e.g., USB D−); identical clamping behavior to CH1 |
| 4 (VP) | Positive Supply Rail Terminal | Acts as anode reference for positive transients; connect to +5 V rail to enable full bidirectional protection |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel I/O protection | Simultaneously safeguards two independent high-speed data lines (e.g., D+/D−) with shared ground and supply terminals |
| Ultra-low 1.8 pF capacitance | Minimizes signal distortion and insertion loss on USB 2.0, DVI, and Ethernet PHY interfaces |
| Bidirectional clamping architecture | Routes ESD energy to either VP (+5 V) or VN (GND) without requiring external bias circuitry |
| IEC 61000-4-2 Level 4 compliance | Validated for ±30 kV contact/air discharge - meets stringent end-equipment ESD certification requirements |
| SOT-143 footprint | Enables compact placement adjacent to I/O connectors, reducing trace inductance and improving surge suppression efficacy |
Applications
| USB 2.0 Interface Protection | DVI Signal Line Protection |
|---|---|
|
Use Scenario: Protecting D+ and D− lines of a USB 2.0 host or device port against user-handling ESD events and cable-discharge transients. IC Role / Device Role / Timing Role: Transient voltage suppressor array providing bidirectional clamping between data lines and system ground/+5 V rail. Use Value: Maintains 480 Mbps signal integrity with <1.8 pF loading while suppressing ±30 kV ESD pulses before they reach the USB transceiver IC. |
Use Scenario: Shielding TMDS clock and data channels on digital video interface connections between graphics cards and flat-panel displays. IC Role / Device Role / Timing Role: Low-capacitance TVS array placed at DVI connector to clamp fast-rising ESD transients on differential pairs. Use Value: Prevents pixel corruption or display lockup by limiting transient overshoot to <12.5 V at 1 A, compatible with DVI's 3.3 V logic swing. |
| 10/100/1000 Ethernet PHY Protection | Notebook Computer I/O Port Protection |
|
Use Scenario: Safeguarding Ethernet transformer-coupled pairs (e.g., TX+/TX−, RX+/RX−) against ESD ingress via RJ45 jacks. IC Role / Device Role / Timing Role: Four-channel TVS solution (using two AOZ8001AJI-05 devices) protecting all four differential data lanes. Use Value: Delivers 18 A surge current capability and <2.5 pF max capacitance - critical for maintaining 1000BASE-T signal eye margin and EMC performance. |
Use Scenario: Integrated ESD protection on notebook motherboard I/O headers including USB, HDMI, and card reader interfaces. IC Role / Device Role / Timing Role: Space-constrained discrete TVS array enabling board-level compliance with IEC 61000-4-2 Level 4 across multiple ports. Use Value: Reduces BOM count and PCB area versus discrete diodes while ensuring consistent clamping behavior across all protected lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TVS diode array applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMA6J5.0A (ON Semiconductor) | Single-channel, 5.0 V VRWM, 600 W peak power, 30 pF typical capacitance - significantly higher capacitance than AOZ8001AJI-05 | Not suitable for >100 Mbps data lines due to excessive capacitive loading; limited to DC/low-speed power rail protection | Select only if protecting non-high-speed lines where capacitance is not critical and dual-channel integration is unnecessary |
| SP1003-050 (Littelfuse) | Quad-channel, 5.0 V VRWM, ±30 kV ESD rating, 0.6 pF typical capacitance - lower capacitance but requires separate ground and VCC pins per channel | Higher pin count (SOT-23-6), larger footprint, and no integrated VP/VN sharing - increases layout complexity for dual-line protection | Prefer when sub-1 pF loading is mandatory and board space allows for additional routing; AOZ8001AJI-05 offers better integration density |
Compared with SMA6J5.0A and SP1003-050, the AOZ8001AJI-05 uniquely balances dual-channel protection, 1.8 pF capacitance, SOT-143 compactness, and shared VP/VN terminals - making it optimal for space-constrained, high-speed 5 V interface designs where layout simplicity and signal fidelity are prioritized.
Availability
AOZ8001AJI-05 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, DVI signal line safeguarding, and notebook computer I/O port hardening requiring stable component supply and guaranteed long-term manufacturability.
Supply support for AOZ8001AJI-05 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Alpha & Omega Semiconductor (AOS) is a fabless power semiconductor company specializing in MOSFETs, TVS diodes, and power ICs for efficiency-critical applications.
The AOZ8001A series was developed specifically for ultra-low-capacitance ESD protection of high-speed digital interfaces - targeting USB, DVI, HDMI, and Ethernet applications where signal integrity and board space are constrained.
FAQ
What is the maximum clamping voltage of the AOZ8001AJI-05 under ESD stress?
The AOZ8001AJI-05 exhibits a maximum clamping voltage (VCL) of 12.5 V at 1 A peak pulse current (IPP), 15.0 V at 5 A IPP, and 16.0 V at 12 A IPP. These values are measured per IEC 61000-4-2 test conditions and ensure downstream ICs remain within safe operating voltage margins during ±30 kV ESD events. The AOZ8001AJI-05 maintains this performance across its full −40°C to +85°C operating range.
Can the AOZ8001AJI-05 be used on 3.3 V data lines?
Yes - the AOZ8001AJI-05 has a 5.5 V working peak reverse voltage (VRWM), which safely accommodates 3.3 V nominal signaling with sufficient margin to prevent leakage or false triggering. Its 8.5 V minimum breakdown voltage (VBR) ensures robust immunity to normal signal swings while still clamping transients above that threshold. The AOZ8001AJI-05 is commonly deployed on 3.3 V USB PHYs and DVI TMDS lines.
How does the AOZ8001AJI-05 differ from the AOZ8001AJI-12 variant?
The AOZ8001AJI-05 is rated for 5 V systems (VRWM = 5.5 V, VBR min = 8.5 V), while the AOZ8001AJI-12 targets 12 V applications (VRWM = 12.5 V, VBR min = 15.0 V). Their clamping voltages differ accordingly: AOZ8001AJI-05 clamps to ≤12.5 V at 1 A, whereas AOZ8001AJI-12 reaches ≤16.0 V. Both share identical 1.8 pF capacitance, SOT-143 package, and ±30 kV ESD rating, but are not interchangeable without verifying system rail voltage compatibility.
What is the recommended PCB layout practice for optimal performance of the AOZ8001AJI-05?
Place the AOZ8001AJI-05 as close as possible to the I/O connector - ideally within 2 mm - with minimal trace length between pins CH1/CH2 and the protected lines. Use short, wide ground traces to VN (pin 1) and connect VP (pin 4) directly to the local +5 V plane. Avoid vias in protection paths and implement a solid ground plane beneath the device to reduce loop inductance. These practices ensure the AOZ8001AJI-05 clamps transients before coupling into adjacent traces.
Does the AOZ8001AJI-05 require external biasing or supporting components?
No - the AOZ8001AJI-05 operates as a self-contained TVS array requiring only direct connections to the protected lines (CH1, CH2), system ground (VN), and +5 V rail (VP). It contains integrated steering diodes and a TVS element; no external capacitors, resistors, or bias networks are needed. This simplifies design and eliminates tuning variables, making the AOZ8001AJI-05 a drop-in solution for dual-line 5 V interface protection.
AOZ8001AJI-05 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Alpha & Omega Semiconductor Inc.
- Package/Case:
- TO-253-4, TO-253AA
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V
- Voltage - Breakdown (Min):
- 8.5V (Typ)
- Voltage - Clamping (Max) @ Ipp:
- 16V
- Current - Peak Pulse (10/1000µs):
- 18A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- Ethernet
- Capacitance @ Frequency:
- 1.8pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-143-4
AOZ8001AJI-05 FAQ
1.How can I place an order for AOZ8001AJI-05 through Aetrix?
Please submit a Request for Quotation (RFQ) for AOZ8001AJI-05 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AOZ8001AJI-05 reliable?
The price and inventory of AOZ8001AJI-05 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AOZ8001AJI-05 is usually 5 days.
3.What payment methods are accepted for AOZ8001AJI-05?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AOZ8001AJI-05 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AOZ8001AJI-05?
AOZ8001AJI-05 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AOZ8001AJI-05 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AOZ8001AJI-05?
For technical support, including AOZ8001AJI-05 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AOZ8001AJI-05 requirements.
6.How does Aetrix verify that AOZ8001AJI-05 is sourced from the original manufacturer or authorized distributors?
All AOZ8001AJI-05 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AOZ8001AJI-05 meets industry standards.
7.What is the process for return or replacement of AOZ8001AJI-05?
All AOZ8001AJI-05 units undergo pre-shipment inspection (PSI). If there is an issue with AOZ8001AJI-05, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AOZ8001AJI-05 part is unused and in its original packaging.
Return procedure for AOZ8001AJI-05:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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