NXP Semiconductors CLRC66302HN,518
- Part No.:
- CLRC66302HN,518
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
CLRC66302HN,518.pdf
- Description:
- IC RFID READER 13.56MHZ 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,894
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Product details
Overview
CLRC66302HN,518 from NXP Semiconductors is a high-performance multi-protocol NFC frontend IC supporting ISO/IEC 14443A/B, FeliCa (JIS X 6319-4), ISO/IEC 15693, ISO/IEC 18092 P2P passive initiator, and EPC Class-1 HF modes. It delivers up to 848 kbit/s transfer speed in MIFARE Classic read/write mode, integrates a 512-byte FIFO buffer, and operates from 3.0 V to 5.5 V supply voltage.
For engineers reviewing the CLRC66302HN,518 datasheet, CLRC66302HN,518 pinout, CLRC66302HN,518 application, or CLRC66302HN,518 equivalent, this page provides verified technical context, exact pin functions for HVQFN32 packaging, confirmed protocol support boundaries, real-world use-value metrics for access control and industrial readers, and two validated alternative parts with documented functional trade-offs.
Technical Context
The CLRC66302HN,518 implements a dual-transmitter analog front-end (TX1/TX2) driving 13.56 MHz antenna circuits without external active components, and handles full ISO/IEC 14443A framing, CRC, and parity in hardware. Its digital module supports MIFARE Classic encryption acceleration and FeliCa demodulation/decoding with 424 kbit/s bidirectional throughput.
It features five independent timers-including Timer4 as an LFO-driven wake-up timer for low-power card detection-and a dedicated SAM interface via separate I²C bus. Host connectivity includes SPI (up to 10 Mbit/s), UART (RS-232–compatible, up to 1228.8 kBd), and dual I²C variants (Fast mode up to 400 kBd, Fast-mode Plus up to 1000 kBd).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0 V to 5.5 V - Enables direct integration into 3.3 V and 5 V industrial power rails without level-shifting. |
| Max Transfer Speed | 848 kbit/s (MIFARE Classic) - Supports high-throughput credential reads in fast-moving access gate applications. |
| FIFO Buffer Size | 512 bytes - Reduces host CPU interrupt frequency and enables burst-mode transaction handling. |
| Operating Temperature | −25 °C to +85 °C - Qualified for deployment in uncontrolled indoor industrial and commercial environments. |
| RF Protocol Support | ISO/IEC 14443A/B, FeliCa, ISO/IEC 15693, ISO/IEC 18092, EPC Class-1 HF - Covers global contactless smartcard, transit, and item-level tagging standards. |
| Host Interfaces | SPI (10 Mbit/s), UART (1228.8 kBd), I²C (400/1000 kBd), plus dedicated SAM I²C - Allows flexible host MCU selection and secure key offloading. |
| Power-Down Current | 8 nA typical - Enables battery-powered handheld readers with multi-week standby life. |
Pinout & Package
HVQFN32 package (5 × 5 × 0.85 mm, wettable flanks, MSL1); thermally enhanced with exposed heatsink pad (Pin 33/VSS) for RF stability and thermal management in compact reader designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX1 / TX2 | RF Transmitter Outputs | Deliver modulated 13.56 MHz carrier to antenna matching network; dual outputs enable differential or diversity antenna configurations. |
| RXP / RXN | Differential RF Receiver Inputs | Accept weak subcarrier-modulated signals from cards; differential topology improves noise immunity in electrically noisy environments. |
| IRQ | Interrupt Request Output | Asserts active-low signal on frame completion, error, card detection, or timer underflow-enables event-driven host firmware. |
| IF0–IF3 | Configurable Host Interface Pins | Multifunction I/O pins dynamically assigned to SPI/I²C/UART per IFSEL0/IFSEL1 settings-reduces PCB routing complexity. |
| PVDD / TVDD / VDD / AVDD / DVDD | Power Supply Terminals | Separated analog/digital/transmitter supplies minimize cross-coupling noise and ensure stable RF performance. |
| XTAL1 / XTAL2 | 27.12 MHz Crystal Oscillator Interface | Drives integrated PLL to generate precise RF clock; eliminates need for external oscillator or frequency synthesizer. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PLL with 27.12 MHz crystal | Eliminates external clock source and reduces BOM cost while guaranteeing RF frequency accuracy per ISO/IEC 14443. |
| Hardware-accelerated MIFARE Classic crypto | Offloads AES-128 and Crypto1 operations from host MCU, enabling faster authentication and reduced firmware overhead. |
| Low-Power Card Detection (LPCD) | Uses Timer4 + LFO to wake system only upon card presence-extends battery life in portable readers without sacrificing responsiveness. |
| Dedicated SAM I²C interface | Isolates secure key storage and cryptographic processing from main host bus, meeting EMV contactless security requirements. |
| 8 programmable GPIOs (OUT0–OUT7) | Support LED control, antenna tuning switching, or status signaling-reduces need for external logic ICs in space-constrained designs. |
Applications
| Access Control Reader | Industrial Asset Tagging |
|---|---|
Use Scenario: Wall-mounted door reader authenticating MIFARE DESFire EV2 credentials at building entrances. IC Role / Device Role / Timing Role: NFC frontend handling RF modulation/demodulation, protocol framing, and crypto acceleration for secure credential validation. Use Value: 12 cm typical read range (per antenna design) enables hands-free operation; 848 kbit/s speed cuts authentication latency below 150 ms. |
Use Scenario: Handheld maintenance scanner reading ISO/IEC 15693 tags on factory machinery for service history lookup. IC Role / Device Role / Timing Role: Vicinity protocol controller managing long-range (up to 50 cm) tag discovery and block-read operations. Use Value: Hardware CRC and FIFO buffering ensure reliable data transfer in electrically noisy plant floors with minimal host intervention. |
| Gaming Kiosk Authentication | Transit Fare Validator |
Use Scenario: Arcade cabinet verifying FeliCa-based Suica or Octopus cards for game session activation. IC Role / Device Role / Timing Role: FeliCa receiver/demodulator and framer executing JIS X 6319-4-compliant transactions at 424 kbit/s. Use Value: Native FeliCa decoding eliminates host-side software parsing; 424 kbit/s throughput enables sub-300 ms card tap-to-play response. |
Use Scenario: Bus fare validator processing ISO/IEC 14443A MIFARE Ultralight tickets during boarding. IC Role / Device Role / Timing Role: Read/write controller executing anti-collision, authentication, and value-write sequences per EMV contactless spec. Use Value: Integrated parity/CRC and ASK modulation circuitry ensures >99.9% transaction success rate in high-vibration mobile environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN5180A0HN/C1 | Single-chip NFC controller with integrated MCU; supports same protocols but adds ARM Cortex-M0+ core and embedded firmware stack. | Reduces host MCU dependency; suitable for standalone readers but increases code ownership and certification burden. | Select PN5180A0HN/C1 when full protocol stack execution on-device is required and host resources are constrained. |
| CLRC66402HN,518 | Successor IC with extended LPCD sensitivity, improved EMI robustness, and backward-compatible pinout and register map. | Enables longer battery life and higher reliability in automotive-grade or outdoor deployments; requires minor firmware update. | Select CLRC66402HN,518 for new designs targeting extended lifecycle, enhanced noise immunity, or future-proofing against obsolescence. |
Compared with PN5180A0HN/C1, CLRC66302HN,518 offers lower system-level BOM cost and simpler host integration for existing protocol stacks, while CLRC66402HN,518 provides measurable improvements in low-power detection and RF stability without architectural change.
Availability
CLRC66302HN,518 is available at Aetrix Electronics and suitable for access control systems, industrial asset tracking terminals, gaming kiosks, and transit fare validators requiring stable component supply across multi-year production cycles.
Supply support for CLRC66302HN,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in contactless communication IP.
The CLRC663 product line was engineered specifically for high-reliability, multi-standard NFC reader applications demanding low power, wide operating temperature, and certified protocol compliance-targeting industrial automation and secure physical access markets.
FAQ
What is the maximum operating distance supported by CLRC66302HN,518?
The CLRC66302HN,518 achieves up to 12 cm typical read range in ISO/IEC 14443A/MIFARE Classic mode, contingent on antenna size, tuning, and environmental conditions. This specification assumes optimized 50 Ω matching network and standard 4-layer PCB layout per NXP reference design AN11751. Range varies with card type and orientation; FeliCa and ISO/IEC 15693 modes yield different distances due to distinct modulation schemes.
Does CLRC66302HN,518 support EMV contactless compliance?
Yes, CLRC66302HN,518 meets EMV contactless protocol specification at the RF physical layer, including field strength, modulation depth, and timing tolerances defined in EMVCo Book 2. Full EMV certification requires system-level validation of host stack, antenna, and mechanical enclosure-but CLRC66302HN,518 provides the necessary RF foundation and protocol acceleration to achieve compliance.
Can CLRC66302HN,518 interface directly with a secure element?
Yes, CLRC66302HN,518 includes a dedicated I²C interface (SCL/SDA pins) exclusively for connecting a Secure Access Module (SAM). This isolated bus handles encrypted key exchange and cryptographic operations offloaded from the main host, satisfying requirements for payment-grade security and enabling separation of secure key storage from application logic.
What host interfaces does CLRC66302HN,518 support, and what are their speed limits?
CLRC66302HN,518 supports SPI (up to 10 Mbit/s), UART (RS-232–compatible, up to 1228.8 kBd), and two I²C variants: standard I²C (up to 400 kBd in Fast mode) and I²CL (up to 1000 kBd in Fast-mode Plus). Interface selection is configured via IFSEL0/IFSEL1 pins, and all share the same IF0–IF3 physical pins with dynamic reassignment.
How does CLRC66302HN,518 handle low-power operation for battery-powered devices?
CLRC66302HN,518 implements three power-saving modes: hard power-down (8 nA typical), standby, and Low-Power Card Detection (LPCD). In LPCD mode, Timer4 driven by the internal LFO wakes the device only upon RF field detection-enabling multi-week battery life in handheld scanners while maintaining sub-100 ms card response time.
Is CLRC66302HN,518 pin-compatible with CLRC66301 or CLRC66303 variants?
CLRC66302HN,518 shares identical HVQFN32 pinout and register mapping with CLRC66301 and CLRC66303, but differs in supply voltage range (3.0–5.5 V vs. 2.5–5.5 V for CLRC66303) and LPCD configuration flexibility. CLRC66303 adds enhanced LPCD registers and smaller-antenna load protocol options, making it functionally superset-but CLRC66302HN,518 remains drop-in compatible for existing 3.3/5 V designs.
CLRC66302HN,518 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- RFID Reader
- Frequency:
- 13.56MHz
- Standards:
- ISO 14443, ISO 15693, 18000-3, MIFARE, NFC
- Interface:
- I2C, SPI, UART
- Voltage - Supply:
- 3V ~ 5.5V
- Operating Temperature:
- -25°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
CLRC66302HN,518 FAQ
1.How can I place an order for CLRC66302HN,518 through Aetrix?
Please submit a Request for Quotation (RFQ) for CLRC66302HN,518 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CLRC66302HN,518 reliable?
The price and inventory of CLRC66302HN,518 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CLRC66302HN,518 is usually 5 days.
3.What payment methods are accepted for CLRC66302HN,518?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CLRC66302HN,518 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CLRC66302HN,518?
CLRC66302HN,518 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CLRC66302HN,518 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CLRC66302HN,518?
For technical support, including CLRC66302HN,518 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CLRC66302HN,518 requirements.
6.How does Aetrix verify that CLRC66302HN,518 is sourced from the original manufacturer or authorized distributors?
All CLRC66302HN,518 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CLRC66302HN,518 meets industry standards.
7.What is the process for return or replacement of CLRC66302HN,518?
All CLRC66302HN,518 units undergo pre-shipment inspection (PSI). If there is an issue with CLRC66302HN,518, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CLRC66302HN,518 part is unused and in its original packaging.
Return procedure for CLRC66302HN,518:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CLRC66302HN,518 Tags

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SL2S2602FTBX
NXP Semiconductors

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ST25DV04K-IER6S3
STMicroelectronics

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ST25DV04K-IER6C3
STMicroelectronics

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LXMSJZNCMD-217
Murata Electronics

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NT3H2111W0FTTJ
NXP Semiconductors

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NT3H2111W0FHKH
NXP Semiconductors

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M24LR04E-RMC6T/2
STMicroelectronics

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ST25DV04KC-JF6D3
STMicroelectronics

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ST25DV64KC-IE6S3
STMicroelectronics
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ST25DV64K-IER6T3
STMicroelectronics

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NT3H2211W0FTTJ
NXP Semiconductors

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NT3H2211W0FHKH
NXP Semiconductors
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