NXP Semiconductors CLRC66303EVJ
- Part No.:
- CLRC66303EVJ
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 36-VFBGA
- Datasheet:
-
CLRC66303EVJ.pdf
- Description:
- MULTI-PROTOCOL FRONTEND WITH SMA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CLRC66303EVJ from NXP Semiconductors is a high-performance multi-protocol NFC frontend IC supporting ISO/IEC 14443A/B, FeliCa (JIS X 6319-4), ISO/IEC 15693, ISO/IEC 18092 P2P passive initiator, and EPC HF modes. It delivers up to 848 kbit/s transfer speed in MIFARE Classic read/write mode, integrates a 512-byte FIFO buffer, and operates from 2.5 V to 5.5 V supply. It is deployed in secure access control terminals requiring robust card detection and low-power operation.
For engineers reviewing the CLRC66303EVJ datasheet, CLRC66303EVJ pinout, CLRC66303EVJ application, or CLRC66303EVJ equivalent, key selection considerations include its dual-transmitter 13.56 MHz analog front-end, dedicated SAM I²C interface, flexible LPCD configuration via LPCD_OPTIONS register, HVQFN32/VFBGA36 package options, and support for MIFARE DESFire EV1/EV2, Ultralight C, and FeliCa at 424 kbit/s.
Technical Context
The CLRC66303EVJ implements a dual-path RF analog front-end with TX1/TX2 transmitters and RXP/RXN differential receiver inputs, enabling simultaneous modulation/demodulation for ISO/IEC 14443A and FeliCa protocols. Its integrated PLL derives system clock from a 27.12 MHz crystal, eliminating external clock sources.
It features a programmable interrupt controller with IRQ0/IRQ1 registers, five independent timers (including Timer4 LFO-based wake-up timer), and hardware-accelerated CRC and framing for ISO/IEC 14443A - handling parity, SOF detection, and frame termination without host intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.5 V to 5.5 V - enables direct integration into battery-powered or wide-input industrial systems without level-shifting. |
| RF Frequency | 13.56 MHz - standard HF ISM band operation compliant with global NFC and contactless smartcard regulations. |
| Max Data Rate | 848 kbit/s (MIFARE Classic) - supports high-throughput credential reads in transit fare collection and secure ID verification. |
| FIFO Size | 512 bytes - reduces host CPU overhead during burst transfers and improves transaction latency in multi-tag polling. |
| Power-Down Current | 8 nA typical - enables ultra-low-power card presence monitoring in always-on access readers. |
| Operating Temp | −40 °C to +105 °C - qualified for industrial-grade deployment in uncontrolled environments like outdoor kiosks and factory gates. |
| Host Interfaces | SPI (10 Mbit/s), I²C (Fast-mode Plus, 1000 kBd), UART (1228.8 kBd) - provides flexible connectivity to microcontrollers with varying peripheral availability. |
Pinout & Package
CLRC66303EVJ is available in HVQFN32 (SOT617-1) and VFBGA36 (SOT1985-1) packages. The HVQFN32 variant features wettable flanks for automated optical solder-joint inspection; the VFBGA36 offers minimal footprint (3.5 mm × 3.5 mm) for space-constrained designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX1 / TX2 | RF Transmitter Outputs | Drive 13.56 MHz carrier to antenna matching network; dual outputs support differential or single-ended antenna configurations. |
| RXP / RXN | Differential RF Receiver Inputs | Accept demodulated signal from antenna; high common-mode rejection improves noise immunity in electrically noisy environments. |
| XTAL1 / XTAL2 | Crystal Oscillator Terminals | Interface directly to 27.12 MHz fundamental-mode quartz crystal; internal PLL eliminates need for external clock generator. |
| IRQ | Interrupt Request Output | Asserts active-low signal on card detection, frame end, timer underflow, or error - enables event-driven host firmware architecture. |
| PDOWN | Power-Down Control Input | Active-high signal entering hard power-down mode with 8 nA quiescent current - critical for battery longevity in portable readers. |
| IFSEL0 / IFSEL1 | Host Interface Selection Inputs | Configure pin multiplexing for SPI/I²C/UART at boot - allows single BOM to support multiple host controller interfaces. |
Key Features
| Feature | Design Value |
|---|---|
| Low-Power Card Detection (LPCD) | Configurable via LPCD_OPTIONS register - extends battery life in handheld readers by minimizing active RF time while maintaining reliable card wake-up. |
| Dedicated SAM I²C Interface | Separate I²C bus (SCL/SDA) for Secure Access Module - isolates cryptographic key storage and crypto operations from main host interface, meeting EMVCo and Common Criteria requirements. |
| FeliCa Protocol Support | Full demodulation, decoding, and framing for JIS X 6319-4 - enables interoperability with Japanese transit cards (e.g., Suica, Pasmo) without external baseband processing. |
| MIFARE Classic Hardware Encryption | On-die support for Crypto1 cipher in read/write mode - accelerates authentication and data exchange with MIFARE Classic 1k/4k cards, reducing host CPU load. |
| Flexible Antenna Tuning | New Load Protocol settings optimized for smaller antennas - improves coupling efficiency and read range in compact form-factor devices like wearable readers and IoT edge nodes. |
Applications
| Access Control Terminal | Gaming Kiosk |
|---|---|
Use Scenario: Contactless credential validation at office building entrances using MIFARE DESFire EV2 cards. IC Role / Device Role / Timing Role: NFC frontend managing RF field generation, protocol framing, and secure SAM communication for mutual authentication. Use Value: Achieves >10 cm read distance with standard PCB antenna and maintains <150 ms total transaction time including SAM-assisted key exchange. | Use Scenario: Player account login and loyalty point redemption on casino floor kiosks using FeliCa-enabled mobile wallets. IC Role / Device Role / Timing Role: Dual-mode initiator supporting both ISO/IEC 14443A (for legacy cards) and FeliCa (for Japanese mobile payments). Use Value: Enables 424 kbit/s FeliCa transactions with sub-200 ms response time, meeting real-time gaming UX requirements. |
| Industrial Asset Tag Reader | Transit Fare Validator |
Use Scenario: Handheld scanner identifying ISO/IEC 15693 ICODE tags on machinery in factory maintenance workflows. IC Role / Device Role / Timing Role: Vicinity protocol reader with configurable listen window and adaptive anti-collision for dense tag environments. Use Value: Reads up to 8 ICODE SLI-X tags within 1.5 seconds using hardware-accelerated inventory commands and CRC checking. | Use Scenario: On-bus validator processing MIFARE Ultralight C tickets and Suica cards in rapid succession during boarding. IC Role / Device Role / Timing Role: Multi-protocol initiator supporting concurrent ISO/IEC 14443A and FeliCa polling with automatic mode switching. Use Value: Sustains >120 validations/hour with zero manual intervention, leveraging hardware FIFO and interrupt-driven host handshaking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC frontend applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN5180A0HN/C | Single-transmitter architecture; no dedicated SAM I²C; supports NFC Forum LLCP but lacks FeliCa demodulation circuitry. | Optimized for Android-compliant peer-to-peer and card emulation; not certified for FeliCa or EMV contactless payment stack. | Choose PN5180A0HN/C for cost-sensitive consumer electronics where FeliCa and SAM isolation are unnecessary. |
| CLRC66403HN | Successor IC with enhanced EMVCo 3.x compliance, extended temperature range (−40 °C to +125 °C), and improved RF sensitivity (+3 dBm RX gain). | Targeted at automotive and harsh-environment deployments requiring AEC-Q100 qualification and higher reliability margins. | Choose CLRC66403HN for new automotive or industrial designs demanding extended lifetime and stricter certification. |
Compared with PN5180A0HN/C, CLRC66303EVJ delivers FeliCa-native support and SAM security isolation essential for transit and banking applications; versus CLRC66403HN, it offers proven maturity and lower unit cost for established industrial access systems where extended temp rating is not required.
Availability
CLRC66303EVJ is available at Aetrix Electronics and suitable for access control terminals, gaming kiosks, industrial asset readers, and transit fare validators requiring stable component supply across multi-year production cycles.
Supply support for CLRC66303EVJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with core expertise in RFID, NFC, and secure element technologies.
The CLRC663 product line was designed to serve as a high-integration, multi-standard NFC frontend for secure contactless infrastructure - targeting applications demanding simultaneous support for legacy MIFARE, regional FeliCa, and emerging ISO/IEC 15693 ecosystems.
FAQ
What is the primary function of the CLRC66303EVJ in an NFC system?
The CLRC66303EVJ serves as the analog and digital front-end for contactless communication, handling RF signal generation, modulation/demodulation, protocol framing (ISO/IEC 14443A/B, FeliCa, ISO/IEC 15693), and host interface bridging. It does not execute application-layer logic but offloads physical and link-layer tasks from the host microcontroller, enabling efficient MIFARE Classic, DESFire, and FeliCa transactions. CLRC66303EVJ integrates dedicated hardware for CRC, parity, SOF detection, and timer-based wake-up - reducing host firmware complexity.
Does CLRC66303EVJ support FeliCa protocol natively, and what is its maximum data rate?
Yes, CLRC66303EVJ natively supports FeliCa (JIS X 6319-4) with integrated demodulation, decoding, and framing circuitry - no external baseband processor is needed. It achieves bidirectional data rates up to 424 kbit/s, matching the performance of dedicated FeliCa readers used in Japanese transit systems. This capability is confirmed in Section 1 (General description) and Table 7 of the datasheet, and applies specifically to the CLRC66303 variant per revision 5.4.
How does the CLRC66303EVJ differ from CLRC66301/02 in terms of power supply and low-power operation?
The CLRC66303EVJ supports a wider supply voltage range of 2.5 V to 5.5 V (vs. 3.0 V–5.5 V for CLRC66301/02), enabling direct compatibility with 2.5 V logic systems and single-cell Li-ion battery operation. It also introduces the LPCD_OPTIONS register for fine-grained control of low-power card detection timing and sensitivity - a feature absent in earlier variants - making CLRC66303EVJ the recommended choice for battery-powered access readers per Section 2 of the datasheet.
What package options are available for CLRC66303EVJ, and how do they impact PCB assembly?
CLRC66303EVJ is offered in HVQFN32 (SOT617-1) with wettable flanks and VFBGA36 (SOT1985-1) with 0.5 mm pitch. The HVQFN32 variant simplifies automated optical inspection (AOI) of solder joints due to exposed flank metallization, improving yield in high-volume manufacturing. The VFBGA36 provides the smallest footprint (3.5 mm × 3.5 mm) for space-constrained portable devices but requires precision stencil printing and reflow profiling. Both packages are MSL2-rated per Table 3.
Can CLRC66303EVJ interface with a Secure Access Module (SAM), and how is this implemented?
Yes, CLRC66303EVJ includes a dedicated, isolated I²C interface (separate SCL/SDA pins) explicitly for connecting a Secure Access Module. This hardware-segregated bus ensures cryptographic key storage and crypto operations occur independently of the main host interface - satisfying EMV contactless protocol requirements and preventing side-channel leakage. The SAM interface operates at Fast-mode Plus speeds (up to 1000 kBd) and is documented in Sections 1 and 2 of the datasheet as a defining feature of the CLRC663 series.
CLRC66303EVJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 36-VFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Type:
- -
- Frequency:
- -
- Standards:
- -
- Interface:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-VFBGA (3.5x3.5)
CLRC66303EVJ FAQ
1.How can I place an order for CLRC66303EVJ through Aetrix?
Please submit a Request for Quotation (RFQ) for CLRC66303EVJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CLRC66303EVJ reliable?
The price and inventory of CLRC66303EVJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CLRC66303EVJ is usually 5 days.
3.What payment methods are accepted for CLRC66303EVJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CLRC66303EVJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CLRC66303EVJ?
CLRC66303EVJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CLRC66303EVJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CLRC66303EVJ?
For technical support, including CLRC66303EVJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CLRC66303EVJ requirements.
6.How does Aetrix verify that CLRC66303EVJ is sourced from the original manufacturer or authorized distributors?
All CLRC66303EVJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CLRC66303EVJ meets industry standards.
7.What is the process for return or replacement of CLRC66303EVJ?
All CLRC66303EVJ units undergo pre-shipment inspection (PSI). If there is an issue with CLRC66303EVJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CLRC66303EVJ part is unused and in its original packaging.
Return procedure for CLRC66303EVJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CLRC66303EVJ Tags

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