onsemi CM1230-02CP
- Part No.:
- CM1230-02CP
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- 4-WFBGA, WLCSP
- Datasheet:
-
CM1230-02CP.pdf
- Description:
- TVS DIODE 3.3VWM 9.8VC 4WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:5,356
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CM1230-02CP from onsemi is a 2-channel, low-capacitance ESD protection diode array in a 4-bump WLCSP (0.96 × 0.96 mm) package, designed for high-speed data lines requiring ≤0.8 pF channel capacitance, ±8 kV IEC61000−4−2 contact ESD protection, and rail-to-rail clamping with integrated VCC-to-GND Zener. It protects LCD/camera serial interfaces in wireless handsets.
For engineers reviewing the CM1230-02CP datasheet, pinout, applications, or equivalent options, this device is selected when differential signal integrity, sub-1 pF loading, and supply-rail self-protection without external bypass capacitors are required in space-constrained mobile I/O ports.
Technical Context
The CM1230-02CP implements dual-channel bidirectional ESD clamping using stacked diode pairs between each I/O pin and VP/VN rails, with an integrated Zener diode across VP–VN to absorb positive transients directly into the supply. Its architecture eliminates need for external decoupling on VP.
It operates over –40°C to +85°C with 3.3 V or 5.5 V supply voltage, delivers <±1.0 µA leakage at 5 V bias, and maintains 0.02 pF typical inter-channel capacitance matching-critical for high-speed differential signaling like MIPI D-PHY.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | 2 independent ESD-protected I/O channels |
| Capacitance (CIN) | 0.8 pF typical per channel - preserves signal rise/fall times in >1 Gbps interfaces |
| ESD Rating | ±8 kV contact / ±15 kV air per IEC61000−4−2 Level 4 - meets smartphone system-level ESD compliance |
| Clamp Voltage (VCL) | +9.8 V (positive) / –1.8 V (negative) at 1 A - limits transient overvoltage seen by protected ICs |
| Supply Range (VP–VN) | 3.3 V to 5.5 V - compatible with standard mobile I/O voltage domains |
| Leakage Current | ±1.0 µA max at 5 V - avoids DC loading on sensitive analog or reference lines |
| Package | WLCSP-4 (0.96 × 0.96 mm, 0.5 mm pitch) - enables direct placement adjacent to connectors or ASIC die |
Pinout & Package
CM1230-02CP uses a 4-bump Wafer-Level Chip Scale Package (WLCSP-4, Case 567CS), 0.96 mm × 0.96 mm footprint, 0.5 mm ball pitch, Pb-free, RoHS-compliant, with OptiGuard coating for assembly reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 | VN | Negative supply rail connection - return path for negative ESD current and Zener cathode |
| B1 | CH2 | Channel 2 I/O terminal - bidirectionally clamped between VN and VP |
| A2 | CH1 | Channel 1 I/O terminal - bidirectionally clamped between VN and VP |
| B2 | VP | Positive supply rail connection - path for positive ESD current and Zener anode |
Key Features
| Feature | Design Value |
|---|---|
| 0.8 pF typical channel capacitance | Enables use on MIPI D-PHY, eDP, and USB 2.0 lines without degrading eye diagram margin |
| 0.02 pF typical channel-to-channel capacitance mismatch | Maintains common-mode rejection and skew control in differential pairs (e.g., LVDS, M-PHY) |
| Integrated VP–VN Zener diode | Eliminates need for external 100 nF bypass capacitor on VCC, reducing BOM count and PCB area |
| OptiGuard coating | Improves solder joint reliability during reflow and thermal cycling in handheld assembly |
| ±15 kV HBM ESD rating | Provides robust handling protection during board assembly and field service operations |
Applications
| Mobile Camera Interface Protection | LCD Display Data Line Protection |
|---|---|
Use Scenario: High-speed MIPI CSI-2 data lanes between baseband processor and camera module in smartphones. IC Role / Device Role / Timing Role: ESD transient suppressor placed inline on D+ and D− differential pairs before the image sensor's input receiver. Use Value: 0.8 pF loading prevents signal integrity degradation at 1.5 Gbps+, while ±8 kV contact rating ensures compliance with IEC61000−4−2 system-level testing. | Use Scenario: Embedded DisplayPort or MIPI DSI lanes driving AMOLED/LTPS panels in compact handsets. IC Role / Device Role / Timing Role: Per-lane ESD clamp on clock and data lanes, mounted within 3 mm of display connector to minimize stub inductance. Use Value: 0.02 pF inter-channel capacitance matching preserves differential timing skew, critical for pixel clock recovery and jitter tolerance. |
| USB 2.0 OTG Port Protection | Wireless Handset Keypad/Touch I/O Protection |
Use Scenario: Mini-AB receptacle on dual-role USB 2.0 ports supporting host/peripheral mode in portable devices. IC Role / Device Role / Timing Role: Dual-channel protector on D+ and D− pins, leveraging same-pinout as legacy USB ESD arrays for drop-in layout reuse. Use Value: Sub-1 pF capacitance avoids USB 2.0 eye mask violations; integrated VP–VN Zener removes need for separate VBUS decoupling cap. | Use Scenario: Matrix keypad scan lines or capacitive touch controller I/O in moisture-prone handheld enclosures. IC Role / Device Role / Timing Role: Low-leakage (±1 µA) ESD clamp on row/column lines, placed near mechanical switches or touch pads. Use Value: ±15 kV HBM rating withstands repeated human contact during manufacturing and end-user operation without parameter drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | 0.85 pF typical CIN, 4-channel, SOT-5X3 package (1.6 × 1.6 mm) | Larger footprint; requires PCB real estate not available in ultra-thin handset bezels | Select when board space allows larger package and 4-channel integration reduces component count |
| ESD7L5.0ST5G | Single-channel, SOD-523, 0.75 pF CIN, no VP–VN Zener | Requires external 100 nF bypass cap on VCC; needs two devices for dual-line protection | Select when cost-per-channel is prioritized over assembly count and supply-rail self-protection |
Compared with TPD2E001DRYR and ESD7L5.0ST5G, the CM1230-02CP uniquely combines 2-channel integration, 0.96 mm² WLCSP size, and supply-rail Zener protection-enabling single-device, zero-bypass-capacitor ESD hardening of compact high-speed interfaces.
Availability
CM1230-02CP is available at Aetrix Electronics and suitable for mobile handset camera modules, LCD display interfaces, and USB 2.0 OTG ports requiring stable component supply, consistent lead-free sourcing, and long-term lifecycle support.
Supply support for CM1230-02CP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and mobile applications.
The CM1230-02CP belongs to onsemi's OptiGuard ESD protection portfolio, engineered specifically for high-data-rate mobile interfaces where minimal capacitive loading and supply-rail self-protection are mandatory design constraints.
FAQ
What is the maximum operating voltage range for the CM1230-02CP?
The CM1230-02CP supports an operating supply voltage (VP − VN) from 3.3 V to 5.5 V, with absolute maximum rating of 6.0 V. This range aligns with standard mobile I/O voltage domains including 3.3 V LDO outputs and 5 V USB VBUS-sourced rails. Operation outside this range may compromise ESD clamping performance or reliability of the CM1230-02CP.
Does the CM1230-02CP require an external bypass capacitor on the VP rail?
No, the CM1230-02CP integrates a Zener diode between VP and VN rails, enabling it to absorb positive ESD transients directly into the supply without needing an external bypass capacitor. This feature reduces BOM count and PCB area-confirmed in the datasheet's Electrical Schematic and Applications section for the CM1230-02CP.
What is the channel-to-channel capacitance matching specification for the CM1230-02CP?
The CM1230-02CP specifies 0.02 pF typical difference in input capacitance between CH1 and CH2, measured at 1 MHz with VP = 3.3 V and VN = 0 V. This tight matching ensures minimal skew in differential signaling paths, making the CM1230-02CP suitable for MIPI D-PHY and other high-speed serial interfaces where common-mode noise rejection is critical.
How many ESD strikes can the CM1230-02CP withstand per I/O pin?
The CM1230-02CP is rated to withstand over 1000 ±12 kV contact ESD strikes per I/O pin under IEC61000−4−2 Level 4 test conditions, with 1-second intervals and continuous test execution. This endurance is validated per the datasheet's footnote * and confirms long-term reliability of the CM1230-02CP in production and field environments.
Is the CM1230-02CP compatible with lead-free reflow profiles?
Yes, the CM1230-02CP uses Pb-free solder balls and is qualified for peak reflow temperatures up to 260°C, complying with JEDEC J-STD-020. Its recommended profile (Figure 6 in the datasheet) specifies maximum dwell time above liquidus as 60 seconds-fully compatible with standard lead-free assembly processes used for the CM1230-02CP.
CM1230-02CP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 4-WFBGA, WLCSP
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 9.8V (Typ)
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 4-WLCSP (0.96x0.96)
CM1230-02CP FAQ
1.How can I place an order for CM1230-02CP through Aetrix?
Please submit a Request for Quotation (RFQ) for CM1230-02CP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CM1230-02CP reliable?
The price and inventory of CM1230-02CP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CM1230-02CP is usually 5 days.
3.What payment methods are accepted for CM1230-02CP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CM1230-02CP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CM1230-02CP?
CM1230-02CP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CM1230-02CP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CM1230-02CP?
For technical support, including CM1230-02CP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CM1230-02CP requirements.
6.How does Aetrix verify that CM1230-02CP is sourced from the original manufacturer or authorized distributors?
All CM1230-02CP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CM1230-02CP meets industry standards.
7.What is the process for return or replacement of CM1230-02CP?
All CM1230-02CP units undergo pre-shipment inspection (PSI). If there is an issue with CM1230-02CP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CM1230-02CP part is unused and in its original packaging.
Return procedure for CM1230-02CP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CM1230-02CP Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

