onsemi CM1230-04CP
- Part No.:
- CM1230-04CP
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- 6-WFBGA, WLCSP
- Datasheet:
-
CM1230-04CP.pdf
- Description:
- TVS DIODE 3.3VWM 9.8VC 6WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:9,635
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Product details
Overview
CM1230-04CP from onsemi is a 4-channel, low-capacitance ESD protection array in a 6-bump WLCSP (1.46 × 0.96 mm) package, featuring 0.8 pF typical channel input capacitance, ±8 kV IEC61000−4−2 contact ESD rating, and integrated VCC-to-GND Zener clamping. It protects high-speed serial interfaces such as LCD and camera data lines in wireless handsets where capacitive loading must remain below 1.5 pF.
For engineers reviewing the CM1230-04CP datasheet, pinout, applications, or equivalent options, key selection criteria include channel count, sub-1 pF capacitance, differential signal matching (0.02 pF I/O-to-GND mismatch), supply rail clamping capability, and CSP-6 mechanical compatibility with fine-pitch mobile PCB layouts.
Technical Context
The CM1230-04CP implements bidirectional ESD clamping per channel using paired diodes steered to VP (positive rail) and VN (ground), with an integrated Zener between VP and VN to absorb positive transients without requiring external bypass capacitors. Its architecture eliminates reliance on board-level decoupling for ESD suppression on the supply rail.
Designed for high-speed signal integrity, it maintains stable capacitance across voltage (0–5 V) and temperature (–40°C to +85°C), with mutual coupling limited to 0.15 pF between adjacent I/O pins-critical for differential pairs like MIPI D-PHY lanes. All four channels share identical electrical characteristics and thermal derating behavior under pulsed ESD stress.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | 4 independent ESD-protected I/O lines |
| Input Capacitance (CIN) | 0.8 pF typical at 1 MHz; enables >500 Mbps data rates without signal rise/fall time degradation |
| ESD Rating (IEC61000−4−2) | ±8 kV contact / ±15 kV air discharge; meets Level 4 system-level immunity requirements |
| Clamp Voltage (VCL) | +9.8 V (positive) / –1.8 V (negative) at 1 A, 8/20 µs pulse; limits transient overvoltage seen by protected IC |
| Supply Rail Protection | Zener diode between VP and VN; absorbs positive ESD strikes directly, removing need for external 0.1 µF VP-to-GND capacitor |
| Operating Voltage Range | VP − VN = 3.3 V to 5.5 V; compatible with standard mobile I/O voltage domains |
| Leakage Current | ±1.0 µA max at 5 V bias; avoids DC loading on sensitive analog or reference lines |
Pinout & Package
CM1230-04CP uses a 6-bump Wafer-Level Chip Scale Package (WLCSP6, Case 567BB), measuring 1.46 × 0.96 mm with 0.25 mm pitch, RoHS-compliant SnAgCu solder balls, and OptiGuard coating for assembly reliability.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| A1 | CH1 | First protected I/O channel; bidirectionally clamped to VP/VN rails |
| B1 | CH2 | Second protected I/O channel; matched capacitance and leakage to CH1 |
| A2 | VP | Positive supply rail connection; integrates Zener for VCC ESD protection |
| B2 | VN | Ground reference rail; common return for all clamp paths and Zener cathode |
| A3 | CH3 | Third protected I/O channel; electrically identical to CH1/CH2 |
| B3 | CH4 | Fourth protected I/O channel; supports full-duplex or dual-lane interface protection |
Key Features
| Feature | Design Value |
|---|---|
| Low Channel Capacitance | 0.8 pF typical ensures minimal distortion of high-frequency signals (e.g., MIPI D-PHY up to 1.5 Gbps) |
| Differential Signal Matching | 0.02 pF max CIN mismatch between I/O pins preserves common-mode rejection in balanced interfaces |
| Integrated Supply Clamping | Zener between VP and VN eliminates need for discrete 0.1 µF ceramic capacitor, saving board area and BOM cost |
| High ESD Endurance | Withstands >1000 ±12 kV contact discharges per IEC61000−4−2 Level 4, verified under continuous test protocol |
| OptiGuard Assembly Coating | Enhances solder joint reliability during reflow and mitigates intermetallic growth in fine-pitch CSP mounting |
Applications
| Mobile LCD Interface Protection | Camera Module Data Lines |
|---|---|
Use Scenario: Protecting 4-lane MIPI D-PHY video bus between application processor and AMOLED display in smartphones. IC Role / Device Role / Timing Role: ESD transient suppressor placed inline on each data lane and clock pair, operating transparently during normal 1.5 Gbps operation. Use Value: 0.8 pF capacitance prevents signal integrity loss; 0.02 pF channel matching maintains skew <10 ps across lanes. | Use Scenario: Shielding 2-lane CSI-2 interface connecting image sensor to baseband SoC in compact camera modules. IC Role / Device Role / Timing Role: Bidirectional ESD clamp on both DATA0/DATA1 and CLK+/CLK− lines, referenced to shared VP/VN rails. Use Value: Integrated VP–VN Zener removes need for separate supply decoupling, reducing component count by one 0.1 µF capacitor per module. |
| USB 2.0 OTG Port Protection | Serial ATA (SATA) Express Lanes |
Use Scenario: Safeguarding D+/D− differential pair and ID pin in smartphone USB On-The-Go ports exposed to frequent cable insertion/removal. IC Role / Device Role / Timing Role: Low-capacitance ESD array protecting three critical nodes with matched CIN to avoid differential skew. Use Value: 0.15 pF mutual capacitance between adjacent pins prevents crosstalk-induced jitter on high-speed toggling signals. | Use Scenario: Protecting SATA Gen3 (6 Gbps) TX/RX differential pairs in ultrabook storage subsystems where layout space is constrained. IC Role / Device Role / Timing Role: Four-channel ESD suppressor applied to two differential lanes (TXP/TXN, RXP/RXN), sharing VP/VN supply rails. Use Value: Sub-1 pF loading avoids violation of SATA impedance tolerance (100 Ω ±10%) and maintains eye diagram margin >30%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | 2-channel, 0.8 pF, ±8 kV IEC61000−4−2, SOT-553 package (1.6 × 1.6 mm) | Larger footprint; lacks integrated VP–VN Zener; requires external bypass capacitor | Select when board space allows larger package and supply rail protection is handled externally |
| ESD7L5.0DT5G | Single-channel, 0.8 pF, ±12 kV HBM, SOD-523 package; no VP/VN rails or multi-channel integration | Requires four discrete devices for same function; no supply rail clamping; higher assembly cost | Select only for legacy designs with single-line routing or where CSP mounting is not feasible |
Compared with TPD2E001DRYR and ESD7L5.0DT5G, the CM1230-04CP delivers integrated 4-channel protection in a 1.46 × 0.96 mm CSP with on-die supply clamping-reducing component count by ≥3 and PCB area by >60% versus discrete alternatives.
Availability
CM1230-04CP is available at Aetrix Electronics and suitable for mobile handset design, high-speed camera interface development, and compact notebook I/O port protection requiring stable component supply, consistent lead-free sourcing, and long-term lifecycle support.
Supply support for CM1230-04CP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient innovation, serving automotive, industrial, cloud, medical, and mobile end markets with differentiated silicon solutions.
The CM1230 family belongs to onsemi's OptiGuard-enabled ESD protection portfolio, engineered specifically for ultra-low-capacitance, multi-channel transient suppression in space-constrained, high-data-rate mobile interfaces.
FAQ
What is the package type and dimensions of the CM1230-04CP?
The CM1230-04CP uses a 6-bump Wafer-Level Chip Scale Package (WLCSP6, Case 567BB) measuring 1.46 mm × 0.96 mm with 0.25 mm ball pitch. It features SnAgCu solder balls, RoHS compliance, and OptiGuard surface treatment for enhanced reflow reliability. The package marking includes "L30" and date code "M", with orientation indicated by a "+" mark near pin A1.
Does the CM1230-04CP require an external bypass capacitor on the VP rail?
No, the CM1230-04CP does not require an external bypass capacitor on the VP rail because it integrates a Zener diode between VP and VN that clamps positive ESD transients directly. This internal protection eliminates the need for a discrete 0.1 µF ceramic capacitor typically used for supply rail ESD absorption, simplifying layout and reducing BOM count.
What is the maximum data rate supported by the CM1230-04CP without signal integrity degradation?
The CM1230-04CP supports data rates up to 1.5 Gbps in differential interfaces such as MIPI D-PHY and CSI-2, enabled by its 0.8 pF typical input capacitance and 0.02 pF channel-to-channel capacitance mismatch. These parameters ensure rise/fall times remain unaffected and jitter accumulation stays within specification limits for high-speed mobile serial links.
How many ESD strikes can the CM1230-04CP withstand before performance degradation?
The CM1230-04CP is rated to withstand over 1000 ±12 kV contact ESD strikes per IEC61000−4−2 Level 4, tested continuously at 1-second intervals in a single run. This endurance is validated under standard conditions (VP = 3.3 V, VN grounded, no external capacitor on VP), confirming robust field reliability for frequently plugged/unplugged interfaces.
Is the CM1230-04CP compatible with lead-free reflow profiles?
Yes, the CM1230-04CP is fully compatible with lead-free reflow profiles, including peak temperatures up to 260°C for ≤60 seconds above liquidus. Its WLCSP6 package uses SnAgCu solder balls and is qualified per J-STD-020 moisture sensitivity level 1 (MSL1), making it suitable for standard Pb-free assembly processes without preconditioning.
CM1230-04CP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 6-WFBGA, WLCSP
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 9.8V (Typ)
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-WLCSP (1.46x0.96)
CM1230-04CP FAQ
1.How can I place an order for CM1230-04CP through Aetrix?
Please submit a Request for Quotation (RFQ) for CM1230-04CP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CM1230-04CP reliable?
The price and inventory of CM1230-04CP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CM1230-04CP is usually 5 days.
3.What payment methods are accepted for CM1230-04CP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CM1230-04CP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CM1230-04CP?
CM1230-04CP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CM1230-04CP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CM1230-04CP?
For technical support, including CM1230-04CP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CM1230-04CP requirements.
6.How does Aetrix verify that CM1230-04CP is sourced from the original manufacturer or authorized distributors?
All CM1230-04CP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CM1230-04CP meets industry standards.
7.What is the process for return or replacement of CM1230-04CP?
All CM1230-04CP units undergo pre-shipment inspection (PSI). If there is an issue with CM1230-04CP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CM1230-04CP part is unused and in its original packaging.
Return procedure for CM1230-04CP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CM1230-04CP Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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