onsemi CM1263-06DE
- Part No.:
- CM1263-06DE
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- 12-UFDFN Exposed Pad
- Datasheet:
-
CM1263-06DE.pdf
- Description:
- TVS DIODE 3.3VWM 9.96VC 12UDFN
- Quantity:
- Payment:

- Shipping:

Inventory:8,884
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Product details
Overview
CM1263-06DE from onsemi is a 6-channel low-capacitance ESD protection array for high-speed serial interfaces, featuring 1.0 pF typical channel capacitance, ±8 kV contact/±15 kV air IEC 61000-4-2 ESD rating, and 0.96 Ω dynamic resistance for fast transient clamping - deployed on MIPI, MDDI, and camera/LCD data lines in mobile handsets.
For engineers reviewing the CM1263-06DE datasheet, pinout, applications, or equivalent options, key selection criteria include channel count (6), input capacitance (≤1.2 pF), clamp voltage under 1 A surge (+9.96 V / −1.6 V), VP–VN operating range (3.3–5.5 V), and UDFN12 package compatibility with high-density mobile PCB layouts.
Technical Context
The CM1263-06DE integrates six bidirectional ESD protection channels using stacked diode architecture referenced to dual supply rails (VP1 and VP2) and common ground (VN). Each channel provides low-leakage operation (≤1 μA total leakage across all channels) and tight capacitance matching (±0.02 pF).
It operates within a −40°C to +85°C ambient range, supports 3.3 V and 5.5 V supply configurations, and delivers sub-1 V forward voltage (0.6–0.95 V at 8 mA) with mutual signal coupling limited to 0.11 pF between adjacent pins - critical for preserving signal integrity on MIPI D-PHY and MDDI links.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | 6 independent ESD protection paths for differential or single-ended high-speed data lines |
| Input Capacitance | 0.88–1.2 pF per channel at 1 MHz - enables >1 Gbps data rates without signal distortion |
| ESD Rating | ±8 kV contact / ±15 kV air per IEC 61000-4-2 - meets industrial and mobile end-equipment immunity requirements |
| Clamp Voltage | +9.96 V (positive) / −1.6 V (negative) at 1 A, 8/20 μs - limits voltage overshoot during ESD events |
| Dynamic Resistance | 0.96 Ω (positive) / 0.5 Ω (negative) - ensures rapid energy dissipation and low clamping overshoot |
| Supply Range | VP–VN = 3.3 V to 5.5 V - compatible with standard mobile I/O voltage domains |
| Leakage Current | ≤1000 nA total for all 6 channels at 3.3 V - prevents DC loading of sensitive analog or high-impedance receivers |
Pinout & Package
CM1263-06DE uses a 12-lead UDFN package (Case 517BD), measuring 2.5 mm × 1.35 mm × 0.55 mm with 0.4 mm pitch and an exposed thermal pad (DAP) connected to VN (ground). The package is Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 4, 6 | VN | Common cathode ground reference for all six ESD channels; tied to PCB ground plane via DAP |
| 2 | CH1 | ESD-protected I/O for channel 1 - bidirectional path between signal line and VP1/VN rails |
| 5 | CH2 | ESD-protected I/O for channel 2 - shares VP2 rail with CH3 and CH4 |
| 7 | CH3 | ESD-protected I/O for channel 3 - shares VP2 rail with CH2 and CH4 |
| 8 | VP2 | Positive supply rail for channels 2, 3, and 4 - must be decoupled to ground near device |
| 9 | CH4 | ESD-protected I/O for channel 4 - shares VP2 rail with CH2 and CH3 |
| 10 | CH5 | ESD-protected I/O for channel 5 - shares VP1 rail with CH1 and CH6 |
| 11 | VP1 | Positive supply rail for channels 1, 5, and 6 - must be decoupled to ground near device |
| 12 | CH6 | ESD-protected I/O for channel 6 - shares VP1 rail with CH1 and CH5 |
| DAP | VN (Ground Pad) | Exposed copper thermal pad on bottom surface - soldered to PCB ground pour for thermal and EMI performance |
Key Features
| Feature | Design Value |
|---|---|
| Low Channel Capacitance | 1.0 pF typical per channel - preserves signal rise/fall times on MIPI D-PHY lanes up to 1.5 Gbps |
| Dual VP Rail Architecture | VP1 powers CH1/CH5/CH6; VP2 powers CH2/CH3/CH4 - enables independent supply domain routing on multi-interface PCBs |
| Tight Capacitance Matching | ±0.02 pF inter-channel variation - minimizes skew and crosstalk in parallel high-speed buses |
| Low Dynamic Resistance | 0.5–0.96 Ω - reduces clamping voltage overshoot and improves system-level ESD robustness |
| Pb-Free & RoHS Compliant | UDFN12 package with matte tin lead finish - supports lead-free reflow profiles and environmental compliance |
Applications
| Mobile Camera Interface Protection | MIPI D-PHY Data Line Protection |
|---|---|
Use Scenario: Protecting high-speed image sensor data lanes (e.g., OV5640, IMX219) in smartphone rear/front camera modules against ESD during handling and operation. IC Role / Device Role / Timing Role: Bidirectional ESD clamp placed directly at connector or sensor interface, referenced to local 1.8 V or 2.8 V power rails. Use Value: Prevents latch-up or damage to image sensor I/O cells while maintaining <1.2 pF loading - essential for 1.2 Gbps MIPI CSI-2 timing compliance. | Use Scenario: Shielding MIPI D-PHY differential pairs (CLK, DATA0–DATA3) in display driver ICs (e.g., NT35521) from electrostatic discharge in foldable handset hinge zones. IC Role / Device Role / Timing Role: Per-lane ESD suppressor with matched capacitance, installed adjacent to display connector to minimize stub length. Use Value: Enables full-speed D-PHY operation (HS mode ≥800 Mbps) without added jitter or eye closure due to parasitic capacitance. |
| MDDI Interface Protection | High-Speed LCD Data Bus Protection |
Use Scenario: Safeguarding Motorola Display Data Interface (MDDI) forward/backward channels in legacy Android handsets and automotive infotainment displays. IC Role / Device Role / Timing Role: Six-channel ESD array covering MDDI primary and secondary data lanes plus control signals, powered from shared 3.3 V rail. Use Value: Maintains MDDI bit error rate (BER) <10⁻¹² under repeated ±8 kV contact discharge by limiting transient overshoot to <10 V. | Use Scenario: Protecting RGB or LVDS data lines driving high-resolution TFT-LCD panels in portable medical monitors and ruggedized tablets. IC Role / Device Role / Timing Role: Low-capacitance shunt protector on each data line, with VN pins tied to system ground and VP rails decoupled locally. Use Value: Ensures stable pixel clock integrity and eliminates ghosting artifacts caused by ESD-induced signal bounce on 24-bit RGB buses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD6E05U06RTER | 6-channel, 0.5 pF typical capacitance, ±12 kV air discharge, single VP rail (no VP1/VP2 split) | Optimized for USB 3.0/PCIe where ultra-low capacitance dominates over multi-rail flexibility | Select when lowest possible loading (<0.6 pF) is required and supply rail partitioning is unnecessary |
| SP1006-06UTG | 6-channel, 0.8 pF typical capacitance, ±30 kV air discharge, SOT-563 package (larger footprint) | Better suited for industrial HMI panels with less stringent board space constraints but higher ESD threat levels | Select when higher air discharge rating (±30 kV) and through-hole or larger SMT compatibility are prioritized over miniaturization |
Compared with TPD6E05U06RTER and SP1006-06UTG, the CM1263-06DE uniquely supports dual VP rail configuration for mixed-voltage interface protection, occupies 35% less PCB area than SOT-563 alternatives, and delivers balanced trade-offs among capacitance (1.0 pF), ESD rating (±15 kV air), and layout flexibility in ultra-thin mobile designs.
Availability
CM1263-06DE is available at Aetrix Electronics and suitable for mobile camera modules, MIPI-based display interfaces, and high-speed LCD data bus protection requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for CM1263-06DE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, high-performance silicon solutions for automotive, industrial, cloud, medical, and mobile applications.
The CM1263-06DE belongs to onsemi's ESD protection portfolio designed specifically for high-speed serial interfaces in space-constrained portable electronics - emphasizing low capacitance, precise clamping, and multi-rail adaptability.
FAQ
What is the maximum operating voltage for CM1263-06DE?
The CM1263-06DE supports an operating supply voltage (VP − VN) up to 6.0 V absolute maximum, with recommended operation between 3.3 V and 5.5 V. This range aligns with standard mobile I/O domains including 3.3 V LDO outputs and 5 V USB-powered subsystems. Exceeding 6.0 V may cause permanent damage, and operation below 3.3 V degrades ESD clamping performance per test data in Table 3.
Does CM1263-06DE require external capacitors on VP1 or VP2 rails?
No, the CM1263-06DE is characterized with VP floating (no external capacitor), and its electrical specifications - including clamp voltage and dynamic resistance - are measured under that condition. However, best practice recommends placing a 100 nF ceramic capacitor between each VP pin (VP1 and VP2) and VN (ground) within 2 mm of the device to stabilize rail impedance during fast transients.
How is the ground connection implemented for CM1263-06DE?
The CM1263-06DE uses four dedicated VN pins (pins 1, 3, 4, 6) plus an exposed thermal pad (DAP) that must be soldered to a solid PCB ground plane. All VN terminals and the DAP are internally connected to the same ground reference. This multi-point grounding reduces inductance and improves high-frequency ESD current return path efficiency - critical for achieving specified ±15 kV air discharge performance.
Can CM1263-06DE protect both differential and single-ended signals?
Yes, the CM1263-06DE protects each channel independently and bidirectionally, making it suitable for both differential pairs (e.g., MIPI D-PHY CLK+/−) and single-ended lines (e.g., camera reset, power enable). Each channel clamps positive and negative transients relative to its associated VP and VN rails, supporting mixed-signal routing without polarity constraints.
What is the thermal pad (DAP) soldering requirement for CM1263-06DE?
The DAP on CM1263-06DE must be fully soldered to a minimum 3 mm² copper area connected to the system ground plane. Reflow profile must meet J-STD-020 moisture sensitivity level (MSL) 1 requirements. Incomplete DAP soldering increases thermal resistance and degrades ESD energy dissipation - verified by reduced clamping performance in system-level IEC 61000-4-2 testing.
CM1263-06DE Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 12-UFDFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 6
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 9.96V (Typ)
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-UDFN (2.5x1.35)
CM1263-06DE FAQ
1.How can I place an order for CM1263-06DE through Aetrix?
Please submit a Request for Quotation (RFQ) for CM1263-06DE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CM1263-06DE reliable?
The price and inventory of CM1263-06DE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CM1263-06DE is usually 5 days.
3.What payment methods are accepted for CM1263-06DE?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CM1263-06DE transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CM1263-06DE?
CM1263-06DE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CM1263-06DE order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CM1263-06DE?
For technical support, including CM1263-06DE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CM1263-06DE requirements.
6.How does Aetrix verify that CM1263-06DE is sourced from the original manufacturer or authorized distributors?
All CM1263-06DE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CM1263-06DE meets industry standards.
7.What is the process for return or replacement of CM1263-06DE?
All CM1263-06DE units undergo pre-shipment inspection (PSI). If there is an issue with CM1263-06DE, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CM1263-06DE part is unused and in its original packaging.
Return procedure for CM1263-06DE:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CM1263-06DE Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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