onsemi CM1293A-02SO
- Part No.:
- CM1293A-02SO
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SC-74, SOT-457
- Datasheet:
-
CM1293A-02SO.pdf
- Description:
- TVS DIODE 3.3VWM 9.9VC SC74
- Quantity:
- Payment:

- Shipping:

Inventory:1,719
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CM1293A-02SO from onsemi is a 2-channel low-capacitance ESD protection array designed for high-speed data lines including HDMI, DVI, and USB2.0 interfaces. It delivers ±8 kV IEC 61000−4−2 contact discharge protection, features 2.0 pF max channel input capacitance, 1.5 pF typical I/O-to-I/O capacitance, and integrated Zener clamping between VP and VN rails to protect supply lines without external bypass capacitors.
For engineers reviewing the CM1293A-02SO datasheet, pinout, applications, or equivalent options, key selection criteria include low loading capacitance for signal integrity, rail-to-rail ESD current steering, clamping voltage under 10 V for system-level robustness, and SC-74 package compatibility with space-constrained PCB layouts.
Technical Context
The CM1293A-02SO implements dual-channel bidirectional ESD protection using series diode pairs per channel that steer transient current to VP or VN supply rails. Its embedded Zener diode (VP–VN) provides active rail clamping, eliminating reliance on external bulk capacitance for ESD energy dissipation.
Each channel supports ±15 kV HBM ESD rating and maintains ≤2.0 pF input capacitance at 1 MHz with 3.3 V bias, enabling use in >480 Mbps USB2.0 and multi-Gbps DVI/HDMI links. The device operates across –40°C to +85°C and withstands 1000+ ±8 kV contact discharges without parameter degradation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating (IEC 61000−4−2) | ±8 kV contact discharge - meets Level 4 immunity for industrial and consumer end-equipment certification |
| Channel Input Capacitance (CIN) | 2.0 pF max at 1 MHz - preserves signal integrity on high-speed differential pairs without added jitter or rise-time degradation |
| I/O-to-I/O Capacitance (CIO) | 1.5 pF typical - minimizes crosstalk between adjacent protected lines in dense port layouts |
| Clamp Voltage (VCL) | +9.9 V / –1.6 V at 1 A, 8/20 µs - limits transient overvoltage seen by downstream PHY or controller ICs |
| Supply Voltage Range (VP–VN) | 3.3 V to 5.5 V - compatible with standard logic supply domains including USB 3.3 V and HDMI 5 V auxiliary rails |
| Leakage Current (ILEAK) | ±1.0 µA max at 5 V - ensures negligible DC loading on sensitive analog or reference inputs |
| Operating Temperature | –40°C to +85°C - qualified for extended industrial temperature operation in set-top boxes and digital displays |
Pinout & Package
CM1293A-02SO is housed in a Pb-free SC-74 (Case 318F) surface-mount package, measuring 2.10 mm × 2.64 mm × 0.96 mm, optimized for compact high-density PCB layouts near connector entry points.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | NC | No internal connection - left unconnected; no routing or grounding required |
| 2 | VN | Negative supply rail (GND) - return path for negative ESD transients and bias reference |
| 3 | CH1 | ESD-protected I/O channel - connects directly to first high-speed signal line (e.g., HDMI TMDS+) |
| 4 | CH2 | ESD-protected I/O channel - connects directly to second high-speed signal line (e.g., HDMI TMDS–) |
| 5 | NC | No internal connection - left unconnected; no routing or grounding required |
| 6 | VP | Positive supply rail (PWR) - clamped by internal Zener to limit rail overshoot during positive ESD events |
Key Features
| Feature | Design Value |
|---|---|
| Zener-supplied rail clamping | Eliminates need for external 0.22 µF VP–GND capacitor while maintaining <10 V clamp under 1 A ESD pulse |
| Low 1.5 pF I/O-to-I/O capacitance | Reduces inter-channel coupling in dual-lane interfaces like HDMI or DVI, preserving differential signal fidelity |
| 2.0 pF max channel input capacitance | Enables use on 480 Mbps USB2.0 and 1.65 Gbps DVI links without measurable signal attenuation at Nyquist frequency |
| 1000+ ESD strike endurance | Validated for continuous operation after 1000× ±8 kV contact discharges - supports long-life field deployment |
| Pb-free and RoHS-compliant | Meets global environmental compliance requirements for consumer electronics and display manufacturing |
Applications
| HDMI Port Protection | DVI Port Protection |
|---|---|
Use Scenario: Protecting TMDS differential pairs in notebook GPU outputs and digital TV receivers against connector-based ESD events. IC Role / Device Role / Timing Role: Bidirectional ESD transient suppressor placed immediately before HDMI connector, with VP tied to 5 V auxiliary rail and VN grounded. Use Value: Maintains <2.0 pF loading per channel to avoid degrading 1.65 Gbps TMDS eye diagrams while delivering ±8 kV system-level immunity. |
Use Scenario: Safeguarding DVI-D dual-link pixel clock and data lanes in LCD monitors and graphics docking stations. IC Role / Device Role / Timing Role: Two-channel ESD array deployed per DVI channel pair (CLK+/CLK–, DATA0+/DATA0–), leveraging low CIO to minimize skew. Use Value: 1.5 pF I/O-to-I/O capacitance prevents timing skew between complementary signals, preserving setup/hold margins at 165 MHz pixel clocks. |
| USB2.0 High-Speed Interface | PCI Express Gen1 Lane Protection |
Use Scenario: ESD hardening of USB2.0 differential data lines (D+/D–) in portable storage devices and host controllers. IC Role / Device Role / Timing Role: Dual-channel protector mounted at USB micro-B or Type-A receptacle, with VP connected to 3.3 V I/O supply. Use Value: 2.0 pF max CIN ensures <1% rise-time degradation at 480 Mbps, meeting USB2.0 electrical compliance without equalization. |
Use Scenario: Adding board-level ESD resilience to PCIe Gen1 x1 lanes in embedded computing modules and add-in cards. IC Role / Device Role / Timing Role: One CM1293A-02SO per PCIe differential pair (TX+/TX– or RX+/RX–), VP referenced to 3.3 V PCIe VCCO rail. Use Value: Clamp voltage of +9.9 V / –1.6 V prevents latch-up in PCIe PHYs during hot-plug ESD events while maintaining PCIe Gen1 AC specs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | Single-channel, 0.85 pF CIN, SOT-553 package - lower capacitance but half the channel count | Requires two units for dual-line protection; smaller footprint but higher assembly cost | Select when ultra-low 0.85 pF loading is mandatory and layout allows discrete placement per line |
| SP1001-02UTG | 2-channel, 0.35 pF CIN, SOT-23-6 - significantly lower capacitance but no integrated VP–VN Zener | Needs external 0.1 µF VP–GND capacitor; better for sub-1 GHz RF lines, less optimal for HDMI/DVI rail integrity | Prefer for RF front-end ESD where minimal capacitance outweighs rail-protection convenience |
Compared with TPD2E001DRYR and SP1001-02UTG, the CM1293A-02SO uniquely balances dual-channel integration, 2.0 pF loading, and self-contained rail clamping-making it optimal for HDMI/DVI/USB2.0 ports where board space, BOM count, and supply rail robustness are co-constrained.
Availability
CM1293A-02SO is available at Aetrix Electronics and suitable for HDMI port protection, DVI interface hardening, and USB2.0 high-speed data line ESD mitigation requiring stable component supply across consumer electronics, digital signage, and industrial display programs.
Supply support for CM1293A-02SO includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensing, and connectivity solutions for automotive, industrial, cloud, and consumer markets.
The CM1293A-02SO belongs to onsemi's low-capacitance ESD protection array product line, engineered specifically for high-speed serial interfaces where signal integrity and compact form factor are critical design constraints.
FAQ
What is the maximum operating voltage range for the CM1293A-02SO?
The CM1293A-02SO supports an operating supply voltage range of 3.3 V to 5.5 V between VP and VN pins. This range aligns with common I/O supply domains used in HDMI (5 V auxiliary), USB2.0 (3.3 V), and DVI interfaces. Operation outside this range may compromise ESD clamping performance or reliability, and absolute maximum ratings specify VP–VN must not exceed 6.0 V under any condition.
Does the CM1293A-02SO require external bypass capacitors on the VP pin?
No, the CM1293A-02SO integrates a Zener diode between VP and VN that actively clamps supply rail transients, eliminating the need for external bypass capacitors in most applications. However, for lowest possible clamp voltage-especially when VP is biased significantly below the Zener breakdown voltage-a 0.22 µF ceramic capacitor between VP and ground is recommended per onsemi application guidance.
How many ESD strikes can the CM1293A-02SO withstand before performance degradation?
The CM1293A-02SO is rated to withstand over 1000 ±8 kV contact discharge ESD strikes per IEC 61000−4−2 Level 4, tested continuously at 1-second intervals. Post-test validation confirms all electrical parameters-including leakage current, capacitance, and clamp voltage-remain within specification, ensuring long-term reliability in high-touch consumer and industrial environments.
What is the significance of the "SO" suffix in CM1293A-02SO?
"SO" denotes the SC-74 package variant of the CM1293A-02SO, corresponding to Case 318F. This 6-pin surface-mount package measures 2.10 mm × 2.64 mm and features two NC pins (pins 1 and 5), distinct from the 4-pin SOT-143-4 ("SR") and 10-pin MSOP-10 ("MR") variants. The SO suffix is essential for correct PCB footprint and thermal design.
Can the CM1293A-02SO be used for protecting PCIe Gen1 differential lanes?
Yes, the CM1293A-02SO is suitable for PCIe Gen1 lane protection due to its 2.0 pF max input capacitance, ±8 kV IEC 61000−4−2 rating, and +9.9 V / –1.6 V clamp voltage at 1 A. When placed at the PCIe edge connector with VP tied to the 3.3 V VCCO rail, it prevents ESD-induced PHY latch-up while maintaining Gen1 AC compliance without signal integrity penalties.
CM1293A-02SO Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SC-74, SOT-457
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- -
- Voltage - Clamping (Max) @ Ipp:
- 9.9V (Typ)
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-74
CM1293A-02SO FAQ
1.How can I place an order for CM1293A-02SO through Aetrix?
Please submit a Request for Quotation (RFQ) for CM1293A-02SO on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CM1293A-02SO reliable?
The price and inventory of CM1293A-02SO are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CM1293A-02SO is usually 5 days.
3.What payment methods are accepted for CM1293A-02SO?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CM1293A-02SO transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CM1293A-02SO?
CM1293A-02SO orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CM1293A-02SO order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CM1293A-02SO?
For technical support, including CM1293A-02SO datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CM1293A-02SO requirements.
6.How does Aetrix verify that CM1293A-02SO is sourced from the original manufacturer or authorized distributors?
All CM1293A-02SO products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CM1293A-02SO meets industry standards.
7.What is the process for return or replacement of CM1293A-02SO?
All CM1293A-02SO units undergo pre-shipment inspection (PSI). If there is an issue with CM1293A-02SO, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CM1293A-02SO part is unused and in its original packaging.
Return procedure for CM1293A-02SO:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CM1293A-02SO Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

