Diodes Incorporated D1213A-02S-7
- Part No.:
- D1213A-02S-7
- Manufacturer:
- Diodes Incorporated
- Category:
- TVS Diodes
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
D1213A-02S-7.pdf
- Description:
- TVS DIODE 3.3VWM 10VC SOT353
- Quantity:
- Payment:

- Shipping:

Inventory:8,653
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Product details
Overview
D1213A-02S from Diodes Incorporated is a 2-channel low-capacitance TVS diode array designed for ESD protection of high-speed data lines, featuring ±15 kV air/±8 kV contact IEC 61000-4-2 compliance, 0.85 pF typical channel capacitance, and clamping voltages of 10.0 V (positive) and –1.7 V (negative) at 1 A, deployed in USB 2.0, HDMI, and SATA interfaces.
For engineers reviewing the D1213A-02S datasheet, D1213A-02S pinout, D1213A-02S application, or D1213A-02S equivalent, key selection criteria include channel capacitance ≤1.2 pF, bidirectional clamping performance under 8/20 µs transients, SOT353 package compatibility with high-density PCB layouts, and AEC-Q101 qualification for automotive-grade reliability.
Technical Context
This dual-channel TVS array uses back-to-back diode configurations between VP and VN rails to provide symmetrical bidirectional transient suppression. Each channel integrates a top diode (CHx to VP) and bottom diode (VN to CHx), enabling rail-to-rail clamping without external biasing.
It operates over –65°C to +150°C, supports supply voltages from 3.3 V to 5.5 V, and maintains leakage current ≤1.0 µA at 5 V while delivering 5 A peak pulse current per channel under 8/20 µs waveform conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating (IEC 61000-4-2) | ±15 kV air, ±8 kV contact - meets industrial and automotive ESD immunity requirements without additional circuitry |
| Channel Capacitance | 0.85 pF typ @ 1 MHz - preserves signal integrity on USB 2.0 (480 Mbps) and HDMI 1.4 differential pairs |
| Clamping Voltage (VCL1) | 10.0 V max @ 1 A, 8/20 µs - limits positive transients below 12 V logic rail tolerance |
| Clamping Voltage (VCL2) | –1.7 V max @ –1 A, 8/20 µs - prevents negative overshoot beyond –2 V, protecting CMOS input stages |
| Reverse Breakdown (VBR) | 6.0 V min @ 1 mA - ensures reliable turn-on before damage threshold of protected ICs |
| Dynamic Resistance | 0.9 Ω typ @ 1 A - enables fast voltage stabilization during sub-nanosecond ESD events |
Pinout & Package
Package: SOT353 - 5-pin, surface-mount plastic package with 0.65 mm pitch, 2.2 mm × 1.35 mm footprint, and 1.0 mm height; moisture sensitivity level 1 per J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CH1) | Channel 1 I/O terminal | Protected signal line input/output for first high-speed interface (e.g., USB D+) |
| 2 (CH2) | Channel 2 I/O terminal | Protected signal line input/output for second high-speed interface (e.g., USB D–) |
| 3 (VN) | Negative power rail connection | Common cathode reference for bottom diodes; tied to system ground or negative supply |
| 4 (NC) | No-connect terminal | Internally unconnected; must remain floating or grounded per layout guidelines to avoid parasitic coupling |
| 5 (VP) | Positive power rail connection | Common anode reference for top diodes; tied to 3.3 V or 5 V supply rail |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional rail-clamped topology | Simultaneous VP- and VN-referenced clamping eliminates need for separate positive/negative TVS devices |
| AEC-Q101 qualified | Validated for automotive infotainment and ADAS interfaces requiring extended temperature operation and reliability |
| 0.85 pF channel capacitance | Enables <1% signal rise-time degradation on 480 Mbps USB 2.0 links with minimal eye-diagram distortion |
| Lead-free, halogen-free, green compound | Complies with RoHS 2 (2011/65/EU) and automotive ELV directive; UL 94V-0 flammability rating |
Applications
| USB 2.0 Interface Protection | HDMI 1.4 Data Lane Protection |
|---|---|
Use Scenario: ESD protection for upstream/downstream USB 2.0 ports on laptops, docking stations, and peripheral hubs. IC Role / Device Role / Timing Role: TVS array placed directly at connector, clamping transients before reaching USB transceiver PHY. Use Value: 0.85 pF capacitance avoids violating USB 2.0 eye mask requirements; ±8 kV contact rating exceeds USB-IF compliance threshold. | Use Scenario: Transient suppression on TMDS clock and data pairs in HDMI 1.4 source/sink devices. IC Role / Device Role / Timing Role: Dual-channel clamp on differential pairs, referenced to 3.3 V supply and ground rails. Use Value: Symmetrical clamping (10.0 V / –1.7 V) prevents DC offset shift and preserves common-mode range of HDMI receivers. |
| SATA III Transmitter Protection | Automotive Infotainment Display Link |
Use Scenario: ESD safeguard for SATA III (6 Gbps) transmitter outputs on motherboards and SSD controllers. IC Role / Device Role / Timing Role: Low-capacitance shunt device on differential TXP/TXN lines, referenced to 3.3 V and GND. Use Value: 1.2 pF max capacitance ensures <0.5 dB insertion loss at 3 GHz, maintaining SATA III jitter budget. | Use Scenario: Robust ESD protection for LVDS or FPD-Link II video data lanes in automotive head units and digital clusters. IC Role / Device Role / Timing Role: AEC-Q101-qualified dual-channel clamp on high-speed serial video buses operating at –40°C to +105°C. Use Value: –65°C to +150°C operating range supports under-hood and display module thermal profiles; ±15 kV air rating covers assembly-line ESD risks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel low-capacitance TVS applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SP1003-02HTG | 0.35 pF typical capacitance; lower clamping (8.5 V / –1.5 V); SOT-23-6 package | Better suited for >5 Gbps interfaces (e.g., PCIe Gen3); requires larger board area | Select when ultra-low capacitance is critical and layout allows SOT-23-6 footprint |
| ESD5Z3.3T5G | Single-channel, 3.3 V standoff; 0.6 pF capacitance; SOD-523 package | Requires two devices per differential pair; no integrated VP/VN rails | Choose only for cost-sensitive, space-tolerant designs where discrete placement is acceptable |
Compared with SP1003-02HTG and ESD5Z3.3T5G, D1213A-02S uniquely balances 0.85 pF capacitance, integrated dual-rail referencing, and AEC-Q101 qualification in SOT353-making it optimal for space-constrained automotive and consumer high-speed interfaces requiring single-device integration.
Availability
D1213A-02S is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI 1.4 data lane safeguarding, and automotive infotainment display link designs requiring stable component supply across production lifecycles.
Supply support for D1213A-02S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability protection, power management, and signal integrity solutions for industrial, automotive, and computing markets.
The D1213A-02S belongs to Diodes' ESD protection product line, engineered specifically for high-speed serial interface robustness-emphasizing low capacitance, rail-to-rail clamping, and AEC-Q101 validation for automotive-grade deployment.
FAQ
What is the maximum recommended trace length between D1213A-02S and the protected connector?
Trace length should be ≤3 mm from each CHx pin to its corresponding connector pad to minimize inductance-induced voltage overshoot during ESD events. Longer traces degrade clamping effectiveness-especially critical for ±15 kV air discharge where peak di/dt exceeds 10 A/ns. Layout must maintain tight coupling between CHx, VP, and VN routing to preserve common-mode rejection.
Does D1213A-02S require external decoupling capacitors on VP or VN pins?
No external decoupling is required on VP or VN for ESD suppression functionality. However, a 100 nF ceramic capacitor between VP and VN near the device improves high-frequency transient response by lowering impedance at the clamping node. This is recommended for systems with >100 MHz noise sources but not mandatory for basic IEC 61000-4-2 compliance.
Can D1213A-02S protect AC-coupled differential signals like HDMI or SATA?
Yes-its rail-referenced architecture functions correctly with AC-coupled lines because clamping occurs relative to VP and VN rails, not signal DC bias. For HDMI TMDS pairs, VP is tied to 3.3 V and VN to ground; the device clamps both positive and negative excursions regardless of common-mode voltage swing (typically 0.8–1.2 V), preserving signal fidelity.
How does thermal derating affect D1213A-02S's 5 A peak pulse rating?
The 5 A rating applies at 25°C ambient; above that, derating follows Figure 2 in DS35755-e.g., at 85°C ambient, peak pulse current drops to ~3.2 A (64% of rated value). This reflects junction temperature rise limiting safe energy absorption; designers must verify worst-case board temperature and adjust system-level surge margin accordingly.
D1213A-02S-7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 10V (Typ)
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- -
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -65°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-353
D1213A-02S-7 FAQ
1.How can I place an order for D1213A-02S-7 through Aetrix?
Please submit a Request for Quotation (RFQ) for D1213A-02S-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for D1213A-02S-7 reliable?
The price and inventory of D1213A-02S-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for D1213A-02S-7 is usually 5 days.
3.What payment methods are accepted for D1213A-02S-7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for D1213A-02S-7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for D1213A-02S-7?
D1213A-02S-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your D1213A-02S-7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for D1213A-02S-7?
For technical support, including D1213A-02S-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your D1213A-02S-7 requirements.
6.How does Aetrix verify that D1213A-02S-7 is sourced from the original manufacturer or authorized distributors?
All D1213A-02S-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that D1213A-02S-7 meets industry standards.
7.What is the process for return or replacement of D1213A-02S-7?
All D1213A-02S-7 units undergo pre-shipment inspection (PSI). If there is an issue with D1213A-02S-7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The D1213A-02S-7 part is unused and in its original packaging.
Return procedure for D1213A-02S-7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
D1213A-02S-7 Tags

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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Diodes Incorporated
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