My Inquiry
My Account
Diodes Incorporated D1213A-02SM-7
- Part No.:
- D1213A-02SM-7
- Manufacturer:
- Diodes Incorporated
- Category:
- TVS Diodes
- Package:
- SC-74A, SOT-753
- Datasheet:
-
D1213A-02SM-7.pdf
- Description:
- TVS DIODE 3.3VWM 10VC SOT25
- Quantity:
- Payment:
- Shipping:
Inventory:19,852
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
D1213A-02SM from Diodes Incorporated is a 2-channel low-capacitance TVS diode array designed for bidirectional ESD protection of high-speed data lines. It delivers ±8 kV contact / ±15 kV air IEC 61000-4-2 ESD immunity, 0.85 pF typical channel capacitance, and clamps transients to ≤10.0 V (positive) and ≥−1.7 V (negative) at 1 A, making it suitable for USB 2.0, HDMI, and SATA interfaces.
For engineers reviewing the D1213A-02SM datasheet, D1213A-02SM pinout, D1213A-02SM application, or D1213A-02SM equivalent, key selection criteria include channel capacitance (<1.2 pF), clamping voltage under 1 A pulse, AEC-Q101 qualification, SOT25 package compatibility, and dual-rail supply operation (VP = 3.3–5.5 V, VN = 0 V reference).
Technical Context
This device implements a dual-channel, rail-to-rail TVS architecture with separate VP (positive supply) and VN (negative/ground reference) terminals. Each channel integrates back-to-back diodes between signal line and VP/VN rails, enabling symmetrical ±ESD clamping independent of signal polarity.
It operates across −65°C to +150°C, supports DC supply voltages from 3.3 V to 5.5 V on VP with VN at 0 V, and maintains leakage <±1.0 µA at 5 V bias - critical for preserving signal integrity in low-power, high-speed serial links.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating (IEC 61000-4-2) | ±8 kV contact, ±15 kV air - meets industrial and consumer interface immunity requirements |
| Channel Capacitance | 0.85 pF typ @ 1 MHz - preserves signal rise/fall times in USB 2.0 (480 Mbps) and HDMI 1.4 channels |
| Clamping Voltage (1 A, 8/20 µs) | +10.0 V (CH→VP), −1.7 V (CH→VN) - limits transient overvoltage to safe levels for 3.3 V/5 V I/O buffers |
| Reverse Breakdown Voltage | 6.0 V min @ 1 mA - ensures robust standoff during normal operation without leakage-induced loading |
| Supply Voltage Range | VP = 3.3–5.5 V, VN = 0 V - compatible with standard logic supply domains and dual-rail ESD architectures |
| Leakage Current | ±0.1 µA typ @ 5 V - avoids DC loading on high-impedance data lines and timing-sensitive receivers |
Pinout & Package
Package: SOT25 (5-pin, 3.0 mm × 1.6 mm × 1.1 mm), lead-free matte tin plating over copper leadframe, JEDEC-compliant moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CH1) | Channel 1 signal input | Protected I/O line - connected to USB D+, HDMI TMDS+, or SATA TX/RX |
| 2 (VN) | Negative supply/reference rail | System ground return path for negative clamping; must be low-inductance connection |
| 3 (CH2) | Channel 2 signal input | Second protected I/O line - used for complementary pair or independent interface |
| 4 (VP) | Positive supply rail | Bias rail for positive clamping; tied to local 3.3 V or 5 V plane, not VCC of host IC |
| 5 (NC) | No connect | Internally unconnected pin - left floating per datasheet; no external tie required |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 qualified | Validated for automotive-grade reliability including temperature cycling, HAST, and ESD stress |
| 0.85 pF typical channel capacitance | Minimizes insertion loss and distortion in 480 Mbps USB 2.0 eye diagrams |
| Dual-rail clamping (VP/VN) | Enables precise clamping thresholds referenced to system supply and ground - no dependency on VCC of protected IC |
| Lead-free & halogen-free "Green" construction | Complies with RoHS 2 (2011/65/EU) and automotive material restrictions (Br+Cl <1500 ppm, Sb <1000 ppm) |
Applications
| USB 2.0 Interface Protection | HDMI 1.4 Data Lane Protection |
|---|---|
Use Scenario: Protecting differential D+/D− lines in portable USB hosts and peripherals against ESD events during hot-plug. IC Role / Device Role / Timing Role: Bidirectional TVS array placed immediately before USB transceiver I/O pins to clamp fast transients before they reach silicon. Use Value: 0.85 pF capacitance prevents signal degradation at 480 Mbps; ±8 kV contact rating exceeds USB-IF compliance requirement. | Use Scenario: Shielding TMDS clock and data channels in flat-panel displays and set-top boxes from handling ESD. IC Role / Device Role / Timing Role: Per-channel clamping device referenced to local 3.3 V and ground, preserving differential swing and common-mode range. Use Value: Low dynamic resistance (0.9 Ω) ensures rapid voltage collapse during ESD, limiting overshoot to <10 V at 1 A pulse. |
| SATA Gen II Transmitter Protection | PCI Express Gen 1 Differential Pair Protection |
Use Scenario: Safeguarding SATA TX outputs in SSD controllers and motherboard southbridge chipsets. IC Role / Device Role / Timing Role: Two-channel ESD suppressor placed at connector side of differential pair, with VP tied to 3.3 V bias rail. Use Value: Clamping voltage ≤10.0 V prevents damage to 3.3 V SATA PHY drivers while maintaining jitter margin via sub-1 pF loading. | Use Scenario: Adding board-level ESD resilience to PCIe Gen 1 x1 slots in embedded computing modules. IC Role / Device Role / Timing Role: Dual-channel TVS on each differential lane (TX+/TX−), referenced to local 3.3 V and chassis ground. Use Value: AEC-Q101 qualification enables use in industrial PCIe carriers requiring extended temperature and reliability validation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel low-capacitance TVS applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SP1003-02HTG | 0.35 pF typical capacitance; lower clamping (8.5 V @ 1 A); SOD-323 package (2-pin per channel) | Higher bandwidth suitability (up to USB 3.0 Gen 1); less PCB area but no integrated dual-rail biasing | Select when ultra-low capacitance is prioritized over integrated VP/VN architecture and space-constrained layouts allow discrete placement |
| ESD5Z3.3T5G | Single-channel, 3.3 V standoff; 0.6 pF capacitance; SOD-523 package; no VP/VN terminals | Requires two devices per differential pair; lacks rail-referenced clamping control; simpler biasing (ground-only) | Choose for cost-sensitive, non-automotive designs where dual-rail precision is unnecessary and layout allows duplication |
Compared with SP1003-02HTG and ESD5Z3.3T5G, D1213A-02SM uniquely provides integrated dual-rail (VP/VN) clamping in a single 5-pin SOT25, enabling precise threshold control and AEC-Q101 compliance - essential for automotive infotainment and industrial HDMI systems.
Availability
D1213A-02SM is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI 1.4 data lane hardening, and SATA Gen II transmitter safeguarding requiring stable component supply across automotive, industrial, and consumer design cycles.
Supply support for D1213A-02SM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability protection, power management, and signal integrity solutions for automotive, industrial, and computing markets.
The D1213A-02SM belongs to Diodes' "Ultra-Low Capacitance TVS Array" product line, engineered specifically for ESD-hardened high-speed serial interfaces where sub-1 pF loading and AEC-Q101 qualification are mandatory.
FAQ
What is the maximum operating temperature range for D1213A-02SM?
The D1213A-02SM is rated for operation from −65°C to +150°C, with full electrical performance guaranteed across this range. Its AEC-Q101 qualification includes temperature cycling, high-accelerated stress testing, and storage life validation at these extremes - making it suitable for under-hood automotive and industrial control environments.
Can D1213A-02SM be used with 5 V logic systems?
Yes - the device supports VP supply voltages up to 5.5 V and maintains specified clamping and leakage performance at 5 V. Its 6.0 V minimum reverse breakdown ensures reliable standoff, and its ±8 kV contact ESD rating meets IEC 61000-4-2 requirements for 5 V interface protection in industrial and consumer equipment.
Is the NC pin (Pin 5) required to be grounded or left floating?
Pin 5 is internally unconnected and must be left floating per the datasheet. Diodes Incorporated explicitly states no external connection is needed or recommended. Grounding or biasing Pin 5 may introduce parasitic coupling or violate thermal/moisture sensitivity specifications defined for the SOT25 package.
How does the dual-rail (VP/VN) architecture improve ESD protection versus single-rail TVS diodes?
The VP/VN architecture enables independent, symmetrical clamping to both positive and negative supply rails - eliminating reliance on the protected IC's VCC and ground. This ensures consistent clamping thresholds regardless of host IC power sequencing, reduces ground bounce sensitivity, and improves transient response time by shortening current loop paths in high-frequency ESD events.
D1213A-02SM-7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Package/Case:
- SC-74A, SOT-753
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 10V (Typ)
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- -
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -65°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-25
D1213A-02SM-7 FAQ
1.How can I place an order for D1213A-02SM-7 through Aetrix?
Please submit a Request for Quotation (RFQ) for D1213A-02SM-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for D1213A-02SM-7 reliable?
The price and inventory of D1213A-02SM-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for D1213A-02SM-7 is usually 5 days.
3.What payment methods are accepted for D1213A-02SM-7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for D1213A-02SM-7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for D1213A-02SM-7?
D1213A-02SM-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your D1213A-02SM-7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for D1213A-02SM-7?
For technical support, including D1213A-02SM-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your D1213A-02SM-7 requirements.
6.How does Aetrix verify that D1213A-02SM-7 is sourced from the original manufacturer or authorized distributors?
All D1213A-02SM-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that D1213A-02SM-7 meets industry standards.
7.What is the process for return or replacement of D1213A-02SM-7?
All D1213A-02SM-7 units undergo pre-shipment inspection (PSI). If there is an issue with D1213A-02SM-7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The D1213A-02SM-7 part is unused and in its original packaging.
Return procedure for D1213A-02SM-7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
D1213A-02SM-7 Tags
-
ESD9B5.0ST5G
onsemi
-
DESD3V3E1BL-7B
Diodes Incorporated
-
ESD5Z3.3T1G
onsemi
-
D5V0H1B2LP-7B
Diodes Incorporated
-
D5V0P1B2LP-7B
Diodes Incorporated
-
DESD5V0U1BA-7
Diodes Incorporated
-
ESD5Z5.0T1G
onsemi
-
DESD5V0U1BB-7
Diodes Incorporated
-
D12V0L1B2LP-7B
Diodes Incorporated
-
PESD2V0Y1BSFYL
Nexperia USA Inc.
-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage
-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
