Diodes Incorporated D5V0L2B3T-7
- Part No.:
- D5V0L2B3T-7
- Manufacturer:
- Diodes Incorporated
- Category:
- TVS Diodes
- Package:
- SOT-523
- Datasheet:
-
D5V0L2B3T-7.pdf
- Description:
- TVS DIODE 5VWM 14VC SOT523
- Quantity:
- Payment:

- Shipping:

Inventory:25,943
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Product details
Overview
D5V0L2B3T-7 from Diodes Incorporated is a 2-channel, bidirectional TVS diode array designed for ESD protection of high-speed data lines in portable electronics. It features 5.0 V reverse working voltage, ≤20 pF channel capacitance at 1 MHz, ±30 kV IEC 61000-4-2 contact/air ESD rating, and 6 A peak pulse current (8/20 µs), deployed in USB 2.0, HDMI, and cellular antenna interfaces.
For engineers reviewing the D5V0L2B3T-7 datasheet, D5V0L2B3T-7 pinout, D5V0L2B3T-7 application, or D5V0L2B3T-7 equivalent, key selection criteria include low-capacitance signal integrity preservation, symmetrical clamping behavior across dual channels, thermal derating above 25°C ambient, and SOT523 footprint compatibility with space-constrained PCB layouts.
Technical Context
This TVS array uses two independent, symmetrical Zener-based clamping diodes sharing a common cathode (Pin 3), enabling bidirectional transient suppression on differential or single-ended lines without polarity constraints. Each channel exhibits 6–8 V breakdown at 1 mA and clamps to ≤9.0 V at 1 A (8/20 µs), with differential resistance under 0.2 Ω during surge conduction.
Its 15–20 pF input capacitance (measured channel-to-common pin at 0 V, 1 MHz) ensures minimal signal distortion on 480 Mbps USB 2.0 or 1.5 Gbps HDMI TMDS lines. The device operates from −65°C to +150°C junction temperature and dissipates up to 200 mW continuously on standard FR-4 pads per Diodes' AP02001 layout.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Working Voltage | 5.0 V - Maximum continuous DC or RMS signal voltage before leakage exceeds 100 nA |
| Breakdown Voltage | 6–8 V @ 1 mA - Threshold where clamping initiates; defines minimum overvoltage margin before protection engages |
| Clamping Voltage | ≤9.0 V @ 1 A - Peak voltage seen by protected IC during 1 A transient; critical for I/O pin survivability |
| Channel Capacitance | 15–20 pF @ 0 V, 1 MHz - Limits insertion loss and rise-time degradation on high-speed serial links |
| ESD Rating | ±30 kV air/contact - Meets highest IEC 61000-4-2 level; qualifies for drop-test ruggedized handheld designs |
| Peak Pulse Current | 6 A (8/20 µs) - Sustains worst-case lightning-induced surges per IEC 61000-4-5 Level 3 |
| Thermal Resistance | 625 °C/W - Junction-to-ambient value on standard 2 oz copper pad; dictates power derating above 25°C |
Pinout & Package
Package: SOT523 - ultra-compact 3-pin surface-mount package (1.60 × 0.80 × 0.50 mm), RoHS-compliant, matte tin-plated Alloy 42 leadframe, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | Channel 1 Anode | Input node for first protected line; connects to data line (e.g., USB D+) |
| Pin 2 | Channel 2 Anode | Input node for second protected line; connects to complementary data line (e.g., USB D−) |
| Pin 3 | Common Cathode | Shared return path to ground; must be routed with low-inductance connection to system GND plane |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping symmetry | Identical ±30 kV ESD performance and <9.0 V clamping on both polarities - eliminates need for polarity-aware routing |
| Ultra-low channel capacitance | 15–20 pF max - preserves signal integrity on 480 Mbps USB 2.0 and 100 Mbps Ethernet PHY interfaces |
| Low differential resistance | <0.2 Ω - minimizes voltage overshoot during fast transients and reduces localized heating |
| SOT523 footprint | 1.60 × 0.80 mm body - enables placement adjacent to connectors in slim smartphone bezels and wearable PCBs |
Applications
| USB 2.0 Interface Protection | HDMI TMDS Line Protection |
|---|---|
Use Scenario: ESD protection for D+/D− differential pair in smartphone USB OTG ports exposed to frequent plug/unplug cycles. IC Role / Device Role / Timing Role: Bidirectional transient voltage suppressor placed within 2 mm of connector, clamping surges before they reach USB PHY IC. Use Value: Prevents latch-up or gate oxide damage in USB transceivers while maintaining <15 pF loading for full-speed 480 Mbps compliance. | Use Scenario: Guarding HDMI 1.4 TMDS clock and data channels against electrostatic discharge during cable mating in set-top boxes. IC Role / Device Role / Timing Role: Low-capacitance TVS array mounted at HDMI receptacle, shunting transients to chassis ground via short trace to Pin 3. Use Value: Enables pass/fail compliance with IEC 61000-4-2 Level 4 without degrading eye diagram margin at 1.65 Gbps. |
| Cellular Antenna Switch Protection | Industrial RS-485 Transceiver Port |
Use Scenario: Protecting RF front-end switch control lines (e.g., antenna diversity switching) in LTE handsets from user-hand ESD events. IC Role / Device Role / Timing Role: Dual-channel TVS placed between baseband processor GPIO and GaAs switch enable pins, referenced to common ground. Use Value: Blocks ±30 kV discharges while adding <20 pF parasitic load-well below 50 pF limit for 26 MHz control signal integrity. | Use Scenario: Safeguarding RS-485 transceiver A/B bus pins in factory automation gateways subjected to field wiring ESD. IC Role / Device Role / Timing Role: Symmetrical clamping device installed at terminal block entry, with Pin 3 tied to isolated system ground. Use Value: Maintains common-mode noise immunity and meets EN 61000-4-2 immunity requirements without distorting differential slew rate. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bidirectional low-capacitance TVS array applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SP1002-02UTG | 0.35 pF lower typical capacitance (14.65 pF), 0.5 V higher VRWM (5.5 V), same SOT523 package | Better suited for 5.5 V tolerant interfaces; slightly tighter clamping tolerance (6.8–8.5 V @ 1 A) | Select when protecting 5.5 V logic rails or requiring sub-15 pF loading on >1 Gbps links |
| ESD5Z5.0T1G | Single-channel, 15 pF max, same 5.0 V VRWM, but only one protected line per device | Requires two devices for dual-line protection; larger total board area than D5V0L2B3T-7's integrated dual-channel design | Choose if board layout allows discrete placement or if channel isolation mandates separate grounding paths |
Compared with SP1002-02UTG and ESD5Z5.0T1G, D5V0L2B3T-7 delivers optimal balance of dual-channel integration, 5.0 V system compatibility, and proven 20 pF ceiling-making it preferred for space-constrained USB/HDMI port designs where shared cathode routing simplifies layout and reduces component count.
Availability
D5V0L2B3T-7 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI TMDS line safeguarding, and cellular antenna switch guarding requiring stable component supply across consumer electronics, industrial HMI, and automotive infotainment programs.
Supply support for D5V0L2B3T-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, headquartered in Plano, Texas, with design and manufacturing operations across Asia and the Americas.
The D5V0L2B3T-7 belongs to Diodes' ESD protection product line, engineered specifically for high-speed digital interface hardening in portable and wireless systems where low capacitance and robust IEC 61000-4-2 compliance are mandatory.
FAQ
What is the maximum recommended trace length between D5V0L2B3T-7 and the protected connector?
For optimal ESD performance, the trace from Pin 1 or Pin 2 to the protected line should not exceed 3 mm, and the trace from Pin 3 to the nearest low-inductance ground plane connection must be ≤2 mm. Longer traces increase inductance, raising clamping voltage during fast transients and risking downstream IC damage.
Can D5V0L2B3T-7 be used to protect a 3.3 V I²C bus?
Yes, D5V0L2B3T-7 is compatible with 3.3 V I²C buses because its 5.0 V reverse working voltage exceeds the 3.3 V rail, and its leakage current remains ≤100 nA at that bias. However, verify that the 6–8 V breakdown does not interfere with I²C pull-up resistor sizing or logic threshold margins in your specific implementation.
Does the SOT523 package require special reflow profile considerations?
Yes-the SOT523's small thermal mass demands precise reflow profiling: peak temperature must stay within 260°C for ≤10 seconds, with ramp-up ≤3°C/s and ramp-down ≤6°C/s. Use stencil aperture reduction (80% area ratio) and verify solder joint voiding via X-ray inspection due to fine pitch and limited solder paste volume.
How does the common cathode configuration affect grounding strategy?
The shared cathode (Pin 3) requires a single, low-impedance connection to the system's clean signal ground-not chassis or power ground-to avoid coupling transients into other circuits. Splitting Pin 3 to separate grounds or routing it through ferrites defeats the device's clamping function and may cause failure during ESD events.
D5V0L2B3T-7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Package/Case:
- SOT-523
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 2
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 14V
- Current - Peak Pulse (10/1000µs):
- 6A (8/20µs)
- Power - Peak Pulse:
- 84W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 15pF @ 1MHz
- Operating Temperature:
- -65°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-523
D5V0L2B3T-7 FAQ
1.How can I place an order for D5V0L2B3T-7 through Aetrix?
Please submit a Request for Quotation (RFQ) for D5V0L2B3T-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for D5V0L2B3T-7 reliable?
The price and inventory of D5V0L2B3T-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for D5V0L2B3T-7 is usually 5 days.
3.What payment methods are accepted for D5V0L2B3T-7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for D5V0L2B3T-7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for D5V0L2B3T-7?
D5V0L2B3T-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your D5V0L2B3T-7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for D5V0L2B3T-7?
For technical support, including D5V0L2B3T-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your D5V0L2B3T-7 requirements.
6.How does Aetrix verify that D5V0L2B3T-7 is sourced from the original manufacturer or authorized distributors?
All D5V0L2B3T-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that D5V0L2B3T-7 meets industry standards.
7.What is the process for return or replacement of D5V0L2B3T-7?
All D5V0L2B3T-7 units undergo pre-shipment inspection (PSI). If there is an issue with D5V0L2B3T-7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The D5V0L2B3T-7 part is unused and in its original packaging.
Return procedure for D5V0L2B3T-7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
D5V0L2B3T-7 Tags

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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Diodes Incorporated
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