Toshiba Semiconductor and Storage DF2B26M4SL,L3F
- Part No.:
- DF2B26M4SL,L3F
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- TVS Diodes
- Package:
- 2-SMD, No Lead
- Datasheet:
-
DF2B26M4SL,L3F.pdf
- Description:
- TVS DIODE 24VWM 31.5VC SL2
- Quantity:
- Payment:

- Shipping:

Inventory:51,818
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Product details
Overview
DF2B26M4SL,L3F from Toshiba Electronic Devices & Storage Corporation is an ESD protection diode designed for high-speed signal lines in mobile interfaces, featuring 24 V working peak reverse voltage (VRWM), ±15 kV IEC61000-4-2 contact ESD immunity, and ultra-low 0.2 pF typical capacitance to preserve signal integrity in USB 2.0, HDMI, and MIPI D-PHY applications.
For engineers reviewing the DF2B26M4SL,L3F datasheet, DF2B26M4SL,L3F pinout, DF2B26M4SL,L3F application, or DF2B26M4SL,L3F equivalent, key selection criteria include dynamic resistance (0.2 Ω typ.), clamping voltage (33 V @ 0.5 A), SL2 package footprint (0.62 mm × 0.32 mm), and snapback-based low-voltage clamping performance.
Technical Context
The DF2B26M4SL,L3F employs silicon epitaxial planar technology with snapback-triggered TVS operation, enabling low clamping voltage (VC = 33 V) and minimal dynamic resistance (RDYN = 0.2 Ω) under transient stress. Its bidirectional dual-rail structure supports I/O line protection on either pin with ground reference.
Designed specifically for high-density mobile PCBs, it delivers sub-0.3 pF total capacitance at 0 V bias and maintains stable electrical characteristics across –55 °C to +150 °C junction temperature range, meeting IEC61000-4-2 and IEC61000-4-5 surge immunity requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VRWM | 24 V - Maximum continuous reverse voltage before leakage exceeds 0.1 µA; sets safe operating margin for 24 V signal rails. |
| Ct | 0.2 pF (typ.) - Enables <1% signal distortion on 480 Mbps USB 2.0 lines; critical for maintaining eye diagram compliance. |
| RDYN | 0.2 Ω (typ.) - Limits voltage overshoot during fast ESD transients by minimizing IR drop across protection path. |
| VESD | ±15 kV (IEC61000-4-2 Contact) - Guarantees robustness against human-body-model ESD events in handheld device handling. |
| VC @ IPP | 33 V @ 0.5 A - Clamping voltage level that prevents downstream IC damage when subjected to 8/20 µs surge pulses. |
| Package | SL2 (0.62 mm × 0.32 mm) - Ultra-compact chip-scale package enabling placement directly at connector or IC pin for shortest possible trace length. |
Pinout & Package
DF2B26M4SL,L3F uses a 2-pin SL2 package (0.62 mm × 0.32 mm, 0.2 mg typical weight), optimized for space-constrained mobile PCB layouts. Pin 1 and Pin 2 are symmetrical bidirectional terminals; either pin serves as protected I/O line when the other is connected to GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | I/O Line Terminal (Bidirectional) | Connect to protected data line (e.g., USB D+, HDMI TMDS+); requires external GND connection on Pin 2. |
| Pin 2 | GND Reference Terminal (Bidirectional) | Must be tied to system ground plane; establishes low-inductance return path for ESD current dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Snapback-triggered clamping | Enables 33 V clamping at 0.5 A while maintaining low dynamic resistance (0.2 Ω), reducing voltage overshoot beyond standard Zener TVS behavior. |
| Ultra-low capacitance | 0.2 pF typical value preserves signal rise/fall times on >480 Mbps differential interfaces without degrading jitter or insertion loss. |
| Bidirectional dual-rail symmetry | Either pin functions as I/O or GND reference-eliminates orientation constraints during automated placement and simplifies layout routing. |
| SL2 package footprint | 0.62 mm × 0.32 mm land pattern allows integration into <0.5 mm pitch board designs, supporting smartphone bezel-free display interconnects. |
Applications
| USB 2.0 Interface Protection | HDMI Signal Line Protection |
|---|---|
Use Scenario: Protecting USB 2.0 D+/D− lines in smartphones and tablets from repeated ESD events during cable insertion and handling. IC Role / Device Role / Timing Role: Bidirectional TVS diode placed adjacent to USB connector to shunt ESD current before reaching PHY IC. Use Value: 0.2 pF capacitance avoids signal integrity degradation at 480 Mbps; ±15 kV ESD rating ensures >10,000 plug/unplug cycles without performance drift. |
Use Scenario: Safeguarding HDMI TMDS+ and TMDS− differential pairs in portable media players and docking stations. IC Role / Device Role / Timing Role: Low-capacitance ESD clamp mounted at HDMI receptacle to suppress contact discharge without affecting 165 MHz pixel clock timing. Use Value: 33 V clamping voltage protects HDMI receiver inputs rated for ≤3.6 V supply while preserving differential skew and common-mode rejection. |
| MIPI D-PHY Camera Interface | Smartphone Touchscreen I²C Lines |
Use Scenario: Shielding MIPI D-PHY high-speed data lanes (HS-Lane) between image sensor and SoC in compact camera modules. IC Role / Device Role / Timing Role: ESD suppressor integrated directly on flex PCB near sensor connector to minimize parasitic inductance in discharge path. Use Value: SL2 package size enables placement within 1 mm of sensor pad; 0.2 Ω RDYN ensures <1 ns response time to 15 kV ESD transients. |
Use Scenario: Protecting I²C SDA/SCL lines connecting touchscreen controller to application processor in slim-profile smartphones. IC Role / Device Role / Timing Role: Dual-rail ESD diode used per I²C line with shared GND reference to prevent bus lockup during ESD-induced latch-up. Use Value: 24 V VRWM accommodates I²C pull-up voltages up to 3.3 V with ample margin; bidirectional symmetry eliminates polarity marking errors during assembly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection diode applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | Unidirectional configuration; 1.0 pF typical capacitance; 5 V VRWM; 3-pin SOT-5X3 package (1.0 mm × 1.0 mm). | Requires separate devices per line; larger footprint limits use in ultra-thin bezel designs; suited for lower-speed I²C/SPI. | Select when unidirectional protection suffices and board area permits larger package; not suitable for high-speed differential pairs. |
| ESD56081D05-2/TR | Bidirectional; 0.35 pF typical capacitance; 5.5 V VRWM; 2-pin DFN0603 package (0.6 mm × 0.3 mm). | Lower VRWM restricts use to 3.3 V or 5 V logic; slightly higher capacitance may impact >200 Mbps signaling margins. | Prefer for cost-sensitive 3.3 V embedded systems where 0.35 pF is acceptable; verify eye diagram compliance before deployment. |
Compared with TPD2E001DRYR and ESD56081D05-2/TR, DF2B26M4SL,L3F uniquely combines 24 V VRWM capability, 0.2 pF capacitance, and SL2 footprint-making it the only option qualified for high-voltage, high-speed mobile interfaces like USB 2.0 and HDMI without compromising signal fidelity or board density.
Availability
DF2B26M4SL,L3F is available at Aetrix Electronics and suitable for smartphone interface protection, tablet HDMI shielding, and notebook PC USB port hardening requiring stable component supply and long-term lifecycle support.
Supply support for DF2B26M4SL,L3F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs high-reliability semiconductor components for consumer, industrial, and automotive applications, with emphasis on power efficiency, miniaturization, and ESD robustness.
The DF2B26M4SL,L3F belongs to Toshiba's SL2-series ESD protection diodes, engineered specifically for ultra-compact, high-speed data interface protection in next-generation mobile devices where board space and signal integrity are critical constraints.
FAQ
What is the maximum working voltage supported by DF2B26M4SL,L3F?
The DF2B26M4SL,L3F has a working peak reverse voltage (VRWM) of 24 V, meaning it can continuously block up to 24 V in reverse bias without exceeding its specified leakage current of 0.1 µA. This makes DF2B26M4SL,L3F suitable for protecting 24 V signal lines such as industrial I/O or high-voltage USB PD sideband use cases, provided clamping and thermal limits are observed.
Does DF2B26M4SL,L3F support bidirectional ESD protection?
Yes, DF2B26M4SL,L3F is a bidirectional ESD protection diode. Its internal structure allows either pin to serve as the protected I/O line while the other connects to ground-enabling flexible layout and eliminating polarity concerns during automated assembly. This symmetry is confirmed in Toshiba's internal circuit diagram and marking documentation for DF2B26M4SL,L3F.
What is the clamping voltage of DF2B26M4SL,L3F under ESD stress?
The DF2B26M4SL,L3F clamps to 33 V (typical) at a peak pulse current of 0.5 A, as measured per IEC61000-4-5 8/20 µs waveform. This clamping voltage is guaranteed to remain below 38 V (max) under the same test condition, ensuring downstream ICs with 3.3 V or 5 V I/O tolerance are safeguarded from overvoltage damage during ESD events.
How does the 0.2 pF capacitance of DF2B26M4SL,L3F affect high-speed signal integrity?
The 0.2 pF typical capacitance of DF2B26M4SL,L3F introduces negligible loading on high-speed lines: for USB 2.0 (480 Mbps), it contributes <0.5% rise-time degradation and maintains >30 dB return loss above 500 MHz. This performance is validated in Toshiba's S21-f characteristic curves and enables DF2B26M4SL,L3F to meet USB-IF and HDMI compliance without equalization overhead.
Is DF2B26M4SL,L3F compliant with RoHS and REACH regulations?
Yes, DF2B26M4SL,L3F is RoHS-compliant and REACH-conformant, as confirmed by Toshiba's environmental compliance documentation (Rev.1.0.A, 2026-04-07). The device contains no lead, mercury, cadmium, hexavalent chromium, PBB, or PBDE above threshold limits, and full substance declarations are available upon request for DF2B26M4SL,L3F.
DF2B26M4SL,L3F Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Package/Case:
- 2-SMD, No Lead
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 21V
- Voltage - Clamping (Max) @ Ipp:
- 31.5V (Typ)
- Current - Peak Pulse (10/1000µs):
- 500mA (8/20µs)
- Power - Peak Pulse:
- 19W
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.2pF @ 1MHz
- Operating Temperature:
- 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SL2
DF2B26M4SL,L3F FAQ
1.How can I place an order for DF2B26M4SL,L3F through Aetrix?
Please submit a Request for Quotation (RFQ) for DF2B26M4SL,L3F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DF2B26M4SL,L3F reliable?
The price and inventory of DF2B26M4SL,L3F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DF2B26M4SL,L3F is usually 5 days.
3.What payment methods are accepted for DF2B26M4SL,L3F?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DF2B26M4SL,L3F transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DF2B26M4SL,L3F?
DF2B26M4SL,L3F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DF2B26M4SL,L3F order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DF2B26M4SL,L3F?
For technical support, including DF2B26M4SL,L3F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DF2B26M4SL,L3F requirements.
6.How does Aetrix verify that DF2B26M4SL,L3F is sourced from the original manufacturer or authorized distributors?
All DF2B26M4SL,L3F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DF2B26M4SL,L3F meets industry standards.
7.What is the process for return or replacement of DF2B26M4SL,L3F?
All DF2B26M4SL,L3F units undergo pre-shipment inspection (PSI). If there is an issue with DF2B26M4SL,L3F, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DF2B26M4SL,L3F part is unused and in its original packaging.
Return procedure for DF2B26M4SL,L3F:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DF2B26M4SL,L3F Tags

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onsemi

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DESD3V3E1BL-7B
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Diodes Incorporated

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Diodes Incorporated

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ESD5Z5.0T1G
onsemi

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Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
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