Toshiba Semiconductor and Storage DF3A3.6CT(TPL3)
- Part No.:
- DF3A3.6CT(TPL3)
- Manufacturer:
- Toshiba Semiconductor and Storage
- Category:
- TVS Diodes
- Package:
- SC-101, SOT-883
- Datasheet:
-
DF3A3.6CT(TPL3).pdf
- Description:
- TVS DIODE 1VWM CST3
- Quantity:
- Payment:

- Shipping:

Inventory:9,544
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Product details
Overview
DF3A3.6CT(TPL3) from Toshiba is a dual-channel ESD protection diode array designed for high-speed data lines, featuring 3.6 V Zener voltage (typ.), ±30 kV IEC61000-4-2 contact discharge immunity, and 110 pF terminal capacitance at 0 V, used in USB 2.0, HDMI, and audio interface protection.
For engineers reviewing the DF3A3.6CT(TPL3) datasheet, DF3A3.6CT(TPL3) pinout, DF3A3.6CT(TPL3) application, or DF3A3.6CT(TPL3) equivalent, key selection criteria include ESD clamping voltage, channel count, package footprint (CST3), capacitance budget, and compliance with IEC61000-4-2 Level 4.
Technical Context
This device integrates two identical unidirectional Zener diodes in a single CST3 package, each with anode tied to common cathode configuration. It operates exclusively as a transient voltage suppressor-clamping ESD pulses above ~3.6 V while maintaining low dynamic impedance (≤130 Ω) and minimal leakage (<10 μA at 1 V).
No DC biasing or regulation function is supported; per Toshiba documentation, DF3A3.6CT(TPL3) is strictly for ESD protection and not rated for constant-voltage or power-dissipation applications. Its 150 mW power rating applies only under transient conditions on FR4 board.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Zener voltage | 3.6 V (typ.) at 5 mA - defines primary clamping threshold for ESD transients |
| ESD immunity | ±30 kV contact discharge (IEC61000-4-2) - meets highest industrial immunity level |
| Terminal capacitance | 110 pF at 0 V, 1 MHz - limits signal distortion on high-speed interfaces ≤480 Mbps |
| Dynamic impedance | ≤130 Ω at 5 mA - ensures fast, low-voltage overshoot during ESD pulse clamping |
| Reverse leakage | <10 μA at 1 V - avoids loading of sensitive analog/digital I/O lines |
| Package | CST3 (1.0 × 0.6 × 0.35 mm) - ultra-compact 3-pin SOT-323 variant enabling space-constrained routing |
Pinout & Package
CST3 package: 1.0 mm × 0.6 mm × 0.35 mm body, 3-terminal surface-mount, tape-and-reel compatible, weight 0.75 mg (typ.).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode 1 | ESD clamp path for first protected line (e.g., USB D+) |
| 2 | Cathode 2 | ESD clamp path for second protected line (e.g., USB D−) |
| 3 | Anode | Common return node tied to system ground or low-impedance reference plane |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel integration | Two independent ESD clamps in one CST3 package - reduces PCB area by >40% vs discrete diodes |
| Ultra-low capacitance | 110 pF typical - preserves signal integrity on USB 2.0 and audio differential pairs |
| High ESD robustness | ±30 kV contact discharge - exceeds IEC61000-4-2 Level 4 without degradation |
| Low leakage current | <10 μA at 1 V reverse bias - prevents I/O voltage shift in battery-powered systems |
Applications
| USB 2.0 Interface Protection | HDMI Data Line Protection |
|---|---|
Use Scenario: Protecting D+ and D− lines of embedded USB peripherals against user-handling ESD events. IC Role / Device Role / Timing Role: Unidirectional ESD clamp placed directly at connector, shunting transients to ground before IC input pins. Use Value: Prevents latch-up or permanent damage to USB transceivers while maintaining <480 Mbps eye diagram integrity. | Use Scenario: Safeguarding TMDS clock and data channels in portable HDMI sources against cable-discharge events. IC Role / Device Role / Timing Role: Low-capacitance bidirectional clamping element (anode grounded, cathodes on signal lines) limiting voltage excursion to ≤5 V. Use Value: Enables HDMI compliance without adding series resistance or degrading rise/fall times beyond spec. |
| Smartphone Audio Jack Protection | Industrial Sensor Interface Protection |
Use Scenario: Shielding stereo headphone/mic lines (L/R/GND/MIC) from ESD during plug insertion/removal. IC Role / Device Role / Timing Role: Dual-diode array clamping each signal to ground, leveraging shared anode for compact layout. Use Value: Eliminates pop/click artifacts and protects codec inputs with sub-110 pF loading per channel. | Use Scenario: Protecting RS-485 or CAN FD transceiver I/O pins in factory-floor equipment exposed to charged personnel or tools. IC Role / Device Role / Timing Role: Fast-response Zener clamp absorbing multi-kV transients before reaching communication ICs. Use Value: Maintains communication uptime in harsh ESD environments without requiring external TVS arrays. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRYR | Single-channel, 0.65 pF typical capacitance, 12 kV IEC61000-4-2 contact | Lower capacitance but half the channel count - requires two devices for dual-line protection | Preferred when ultra-low capacitance (<1 pF) is critical and board space allows duplication |
| ESD9X3.3SCT5G | 3.3 V Zener voltage, 15 pF capacitance, ±22 kV IEC61000-4-2 contact | Lower clamping voltage and tighter tolerance, but reduced ESD margin vs DF3A3.6CT(TPL3) | Selected where lower clamping threshold is needed to protect 3.3 V logic rails with tighter VIL/VIH margins |
Compared with TPD2E001DRYR and ESD9X3.3SCT5G, DF3A3.6CT(TPL3) delivers higher ESD immunity (±30 kV) and integrated dual-channel topology in a smaller footprint, making it optimal for cost- and space-constrained USB/audio designs where 3.6 V clamping aligns with 5 V tolerant I/O.
Availability
DF3A3.6CT(TPL3) is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI data line safeguarding, and smartphone audio jack ESD mitigation requiring stable component supply and long-term production continuity.
Supply support for DF3A3.6CT(TPL3) includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Toshiba Electronic Devices & Storage Corporation designs and manufactures discrete semiconductors, power devices, and logic ICs with focus on reliability, miniaturization, and energy efficiency.
DF3A3.6CT(TPL3) belongs to Toshiba's ESD protection diode family engineered specifically for high-density consumer electronics interfaces, emphasizing ultra-small packaging and certified IEC-level immunity without compromising signal fidelity.
FAQ
What is the primary function of DF3A3.6CT(TPL3)?
DF3A3.6CT(TPL3) is a dual-channel unidirectional ESD protection diode array. Its sole function is transient suppression-clamping electrostatic discharge events up to ±30 kV (IEC61000-4-2 contact) on high-speed signal lines. Toshiba explicitly states it must not be used for voltage regulation, constant-current operation, or any non-ESD application. DF3A3.6CT(TPL3) relies on Zener breakdown at ~3.6 V to divert surge current safely to ground.
Does DF3A3.6CT(TPL3) support bidirectional signal lines like USB D+ and D−?
Yes-DF3A3.6CT(TPL3) supports bidirectional data lines via its dual-cathode/anode configuration: pins 1 and 2 serve as separate cathodes for D+ and D−, while pin 3 (anode) connects to ground. This arrangement provides symmetrical clamping for positive and negative ESD transients on both lines without polarity restrictions. DF3A3.6CT(TPL3) maintains 110 pF capacitance per channel, preserving USB 2.0 signal integrity.
What is the maximum operating temperature for DF3A3.6CT(TPL3)?
The junction temperature limit for DF3A3.6CT(TPL3) is 150°C, and the storage temperature range spans −55°C to +150°C. However, continuous operation near absolute maximum ratings degrades reliability. Toshiba mandates derating per their Reliability Handbook-especially under thermal cycling or high-humidity conditions. DF3A3.6CT(TPL3) is rated for 150 mW power dissipation only on FR4 boards (10 mm × 10 mm × 1 mm), not under sustained DC load.
Can DF3A3.6CT(TPL3) replace a standard Zener diode in voltage regulation circuits?
No-Toshiba explicitly prohibits using DF3A3.6CT(TPL3) for voltage regulation or constant-voltage applications. The datasheet states: "This product is for protection against electrostatic discharge (ESD) only and is not intended for any other usage, including without limitation, the constant voltage diode application." DF3A3.6CT(TPL3) lacks guaranteed Zener tolerance, stability under DC bias, or thermal regulation capability required for regulation use.
Is DF3A3.6CT(TPL3) RoHS compliant and lead-free?
Yes-DF3A3.6CT(TPL3) complies with the EU RoHS Directive and is lead-free. Toshiba confirms environmental compliance in the "Restrictions on Product Use" section and advises contacting sales representatives for full material declarations. DF3A3.6CT(TPL3) uses standard SnAgCu solder-compatible terminations and meets JEDEC MSL-1 handling requirements for moisture sensitivity.
DF3A3.6CT(TPL3) Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Toshiba Semiconductor and Storage
- Package/Case:
- SC-101, SOT-883
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 1V
- Voltage - Breakdown (Min):
- 3.1V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 110pF @ 1MHz
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- CST3
DF3A3.6CT(TPL3) FAQ
1.How can I place an order for DF3A3.6CT(TPL3) through Aetrix?
Please submit a Request for Quotation (RFQ) for DF3A3.6CT(TPL3) on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DF3A3.6CT(TPL3) reliable?
The price and inventory of DF3A3.6CT(TPL3) are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DF3A3.6CT(TPL3) is usually 5 days.
3.What payment methods are accepted for DF3A3.6CT(TPL3)?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DF3A3.6CT(TPL3) transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DF3A3.6CT(TPL3)?
DF3A3.6CT(TPL3) orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DF3A3.6CT(TPL3) order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DF3A3.6CT(TPL3)?
For technical support, including DF3A3.6CT(TPL3) datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DF3A3.6CT(TPL3) requirements.
6.How does Aetrix verify that DF3A3.6CT(TPL3) is sourced from the original manufacturer or authorized distributors?
All DF3A3.6CT(TPL3) products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DF3A3.6CT(TPL3) meets industry standards.
7.What is the process for return or replacement of DF3A3.6CT(TPL3)?
All DF3A3.6CT(TPL3) units undergo pre-shipment inspection (PSI). If there is an issue with DF3A3.6CT(TPL3), returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DF3A3.6CT(TPL3) part is unused and in its original packaging.
Return procedure for DF3A3.6CT(TPL3):
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DF3A3.6CT(TPL3) Tags

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