Diodes Incorporated DRTR5V0U2SRQ-7
- Part No.:
- DRTR5V0U2SRQ-7
- Manufacturer:
- Diodes Incorporated
- Category:
- TVS Diodes
- Package:
- TO-253-4, TO-253AA
- Datasheet:
-
DRTR5V0U2SRQ-7.pdf
- Description:
- Dataline Protection PP SOT143 T&
- Quantity:
- Payment:

- Shipping:

Inventory:4,398
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Product details
Overview
DRTR5V0U2SRQ from Diodes Incorporated is a two-channel, low-capacitance TVS diode array designed for high-speed data line ESD protection. It features 1.0 pF typical I/O-to-GND capacitance, ±24 kV IEC 61000-4-2 contact/air ESD rating, 5.5 V reverse standoff voltage, and AEC-Q101 qualification for automotive use - deployed in USB 2.0 and Ethernet PHY interfaces.
For engineers reviewing the DRTR5V0U2SRQ datasheet, DRTR5V0U2SRQ pinout, DRTR5V0U2SRQ application, or DRTR5V0U2SRQ equivalent, key selection criteria include channel capacitance ≤1.5 pF at 1 MHz, clamping voltage ≤13.0 V at 1 A, dual-channel layout in SOT143, and automotive-grade reliability per AEC-Q101.
Technical Context
This device implements two independent bidirectional TVS channels between I/O pins and GND, with no internal connection to VCC in normal operation - VCC pin serves only as an auxiliary terminal for layout symmetry and thermal relief. Each channel delivers symmetrical ±24 kV ESD immunity and clamps transients within 10.5–17.5 V across 1–5 A peak pulse current (8/20 µs).
Its 1.0 pF typical input capacitance enables signal integrity preservation on 480 Mbps USB 2.0 lines, while the 6.0–9.5 V breakdown range ensures robust triggering before IC damage thresholds. The SOT143 package supports high-density routing with 0.009 g mass and JEDEC Level 1 moisture sensitivity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VRWM | 5.5 V - Maximum continuous operating voltage without leakage exceeding 100 nA; sets upper limit for protected signal swing. |
| IPP Max | 5 A - Peak pulse current handling per channel under 8/20 µs waveform; defines surge energy absorption capability. |
| C(I/O–GND) | 1.0 pF typ - Low input capacitance preserves signal rise time and minimizes insertion loss on high-speed interfaces. |
| VCL @ 1A | 10.5–13.0 V - Clamping voltage range during 1 A transient; determines maximum stress imposed on downstream ICs. |
| ESD Rating | ±24 kV air/contact - Complies with IEC 61000-4-2 Level 4; eliminates need for external ESD test margining. |
| VBR (I/O–GND) | 6.0–9.5 V - Reverse breakdown threshold at 1 mA; ensures reliable turn-on before logic-level damage occurs. |
| RDYN | 0.9 Ω typ - Dynamic resistance during clamping; lower value improves voltage regulation under fast transients. |
Pinout & Package
Package: SOT143 - 4-pin surface-mount plastic package with matte tin-plated Alloy 42 leadframe, UL 94V-0 rated molding compound, and JEDEC Level 1 moisture sensitivity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VCC) | Auxiliary terminal / thermal pad anchor | No functional connection in standard configuration; used for PCB thermal relief and mechanical stability. |
| 2 (I/O2) | Protected data line channel 2 | Bidirectional ESD path between I/O2 and GND; shares same electrical specs as Pin 3. |
| 3 (GND) | Common reference and return path | Low-inductance ground connection essential for effective clamping; must be tied directly to system ground plane. |
| 4 (I/O1) | Protected data line channel 1 | Independent bidirectional ESD path between I/O1 and GND; electrically identical to Pin 2. |
Key Features
| Feature | Design Value |
|---|---|
| Two independent ESD protection channels | Enables simultaneous protection of differential or separate high-speed lines (e.g., USB D+/D−) without crosstalk coupling. |
| 1.0 pF typical I/O-to-GND capacitance | Maintains <1% signal distortion on 480 Mbps USB 2.0 eye diagrams; avoids timing skew in matched-pair layouts. |
| AEC-Q101 qualified | Validated for automotive infotainment and ADAS subsystems requiring -55°C to +150°C operation and PPAP compliance. |
| ±24 kV IEC 61000-4-2 ESD immunity | Meets highest industrial ESD robustness class without external shielding or layout derating. |
| SOT143 footprint compatibility | Supports automated placement with standard 0.95 mm pitch pick-and-place nozzles; reduces assembly cost vs. larger packages. |
Applications
| USB 2.0 Interface Protection | Ethernet PHY Port Protection |
|---|---|
Use Scenario: Protecting D+ and D− lines of embedded USB 2.0 host/device ports against connector-induced ESD events during hot-plug. IC Role / Device Role: Bidirectional transient voltage suppressor placed immediately adjacent to USB connector. Use Value: Prevents latch-up or gate oxide damage in USB transceivers while maintaining 480 Mbps data integrity via 1.0 pF channel capacitance. |
Use Scenario: Safeguarding MDI/MDI-X differential pairs in 10/100BASE-TX Ethernet PHYs against cable discharge events. IC Role / Device Role: Dual-channel TVS array connected between each twisted pair and chassis ground. Use Value: Limits induced common-mode surges to <13.0 V at 1 A, preserving PHY receiver input tolerance without degrading signal jitter. |
| Automotive Infotainment Display Link | Industrial Camera Interface Protection |
Use Scenario: Shielding LVDS or FPD-Link II video data lanes in automotive head units from ESD during service port access. IC Role / Device Role: Channel-isolated TVS array mounted at display cable connector entry point. Use Value: AEC-Q101 qualification ensures stable performance across -40°C to +105°C ambient; 1.0 pF capacitance prevents pixel clock skew. |
Use Scenario: Securing MIPI CSI-2 differential lanes in factory automation cameras exposed to operator-handled cables. IC Role / Device Role: Dual-channel ESD clamp on each data lane (CLK, DATA0–DATA3) referenced to local ground. Use Value: Enables >100,000 connect/disconnect cycles without degradation; clamping voltage stays below 13.0 V at full 5 A surge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel TVS diode array applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SP1006-02UTG | Higher 3.5 pF capacitance; 12 V clamping at 1 A; SOD-323 package. | Less suitable for >480 Mbps interfaces; better for lower-speed UART/CAN lines. | Select when board space is constrained but speed requirements are ≤12 Mbps. |
| ESD5Z5.0T1G | Single-channel; 0.6 pF capacitance; 5.0 V VRWM; SOD-523 package. | Requires two devices for dual-line protection; lacks integrated dual-channel layout. | Choose only if discrete channel isolation is required or SOT143 footprint is unavailable. |
Compared with SP1006-02UTG and ESD5Z5.0T1G, DRTR5V0U2SRQ uniquely balances ultra-low capacitance (1.0 pF), dual-channel integration in SOT143, and AEC-Q101 qualification - making it optimal for automotive and high-speed USB/Ethernet designs where layout density and signal fidelity are critical.
Availability
DRTR5V0U2SRQ is available at Aetrix Electronics and suitable for USB 2.0 interface protection, automotive infotainment systems, and industrial camera interfaces requiring stable component supply and long-term lifecycle support.
Supply support for DRTR5V0U2SRQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability protection, power management, and signal integrity solutions for automotive, industrial, and consumer markets.
The DRTR5V0U2SRQ belongs to Diodes' TVS Diode Array product line, engineered specifically for high-speed data line ESD protection in space-constrained, mission-critical applications demanding AEC-Q101 compliance.
FAQ
Is DRTR5V0U2SRQ suitable for USB 3.0 or higher-speed interfaces?
No. Its 1.0 pF typical capacitance is optimized for USB 2.0 (480 Mbps) and 100BASE-TX Ethernet. USB 3.0 (5 Gbps) requires sub-0.3 pF capacitance to avoid signal integrity loss; this device's bandwidth limit is ~3 GHz, insufficient for SuperSpeed signaling.
What is the role of the VCC pin (Pin 1) in DRTR5V0U2SRQ?
Pin 1 (VCC) is not electrically connected to internal TVS junctions. It serves solely as a mechanical and thermal anchor - providing solder joint strength and heat dissipation path to the PCB. No external bias or connection is required or recommended.
Does DRTR5V0U2SRQ require series impedance matching on protected lines?
No. Its low dynamic resistance (0.9 Ω typ) and minimal capacitance eliminate the need for series resistors. However, PCB trace length between the device and protected IC should be ≤5 mm to maintain low-inductance clamping paths and prevent voltage overshoot.
Can DRTR5V0U2SRQ replace older Diodes TVS arrays like D2555-04SLP?
Only in dual-channel, low-capacitance applications. D2555-04SLP has 0.8 pF capacitance but uses SLP1610 package and lacks AEC-Q101 qualification. DRTR5V0U2SRQ offers superior automotive compliance and identical SOT143 footprint, but slightly higher clamping voltage (10.5 V vs. 9.5 V at 1 A).
DRTR5V0U2SRQ-7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Package/Case:
- TO-253-4, TO-253AA
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 7V
- Current - Peak Pulse (10/1000µs):
- 5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- DVI, HDMI, USB
- Capacitance @ Frequency:
- 1pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-143
DRTR5V0U2SRQ-7 FAQ
1.How can I place an order for DRTR5V0U2SRQ-7 through Aetrix?
Please submit a Request for Quotation (RFQ) for DRTR5V0U2SRQ-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DRTR5V0U2SRQ-7 reliable?
The price and inventory of DRTR5V0U2SRQ-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DRTR5V0U2SRQ-7 is usually 5 days.
3.What payment methods are accepted for DRTR5V0U2SRQ-7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DRTR5V0U2SRQ-7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DRTR5V0U2SRQ-7?
DRTR5V0U2SRQ-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DRTR5V0U2SRQ-7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DRTR5V0U2SRQ-7?
For technical support, including DRTR5V0U2SRQ-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DRTR5V0U2SRQ-7 requirements.
6.How does Aetrix verify that DRTR5V0U2SRQ-7 is sourced from the original manufacturer or authorized distributors?
All DRTR5V0U2SRQ-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DRTR5V0U2SRQ-7 meets industry standards.
7.What is the process for return or replacement of DRTR5V0U2SRQ-7?
All DRTR5V0U2SRQ-7 units undergo pre-shipment inspection (PSI). If there is an issue with DRTR5V0U2SRQ-7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DRTR5V0U2SRQ-7 part is unused and in its original packaging.
Return procedure for DRTR5V0U2SRQ-7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DRTR5V0U2SRQ-7 Tags

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onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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DESD5V0U1BA-7
Diodes Incorporated

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ESD5Z5.0T1G
onsemi

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Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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Diodes Incorporated
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