onsemi ESD5381MUT5G
- Part No.:
- ESD5381MUT5G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- 0201 (0603 Metric)
- Datasheet:
-
ESD5381MUT5G.pdf
- Description:
- TVS DIODE 3VWM 10.5VC 2X3DFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,951
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Product details
Overview
ESD5381MUT5G from onsemi is a unidirectional ESD protection diode in X3DFN2 package (0.60 mm × 0.30 mm, 0.3 mm height), rated for 3.0 V working peak reverse voltage, 10.5 V clamping voltage at 1 A pulse, and <1 ns response time. It delivers IEC 61000−4−2 Level 4 (±8 kV contact) and IEC 61000−4−4 Level 4 EFT protection for high-speed data lines in space-constrained portable electronics.
For engineers reviewing the ESD5381MUT5G datasheet, pinout, applications, or equivalent options, key selection criteria include clamping voltage under 8 kV ESD stress, sub-12 pF capacitance, low leakage (<100 nA @ 3.0 V), MSL 1 reflow compatibility, and unidirectional polarity for USB/MIPI signal line protection.
Technical Context
The ESD5381MUT5G is a silicon avalanche diode optimized for transient suppression on low-voltage, high-speed interfaces. Its unidirectional configuration provides forward conduction path only from anode to cathode, enabling precise placement on signal lines where ground-referenced clamping is required.
It operates with 6.1 V minimum breakdown voltage at 1 mA test current and achieves 10.5 V maximum clamping voltage during 8 kV IEC 61000−4−2 contact discharge events. The device's 12 pF typical capacitance and <1 ns response ensure minimal signal distortion on USB 2.0, HDMI, or MIPI D-PHY lanes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Working Peak Reverse Voltage | 3.0 V - sets maximum continuous DC bias before leakage rises significantly; matches 3.3 V rail-tolerant I/Os |
| Clamping Voltage @ 1 A | 10.5 V max - limits transient overvoltage seen by protected IC during ±8 kV ESD event |
| Capacitance | 12 pF typ - preserves signal integrity on 480 Mbps USB 2.0 or 1.5 Gbps MIPI D-PHY links |
| Response Time | <1 ns - ensures clamping activation before ESD energy couples into sensitive circuitry |
| Leakage Current @ VRWM | 100 nA max - avoids loading of high-impedance sensor or reference inputs |
| ESD Rating | IEC 61000−4−2 Level 4 (±8 kV contact) - meets industrial and consumer end-equipment compliance requirements |
| EFT Rating | IEC 61000−4−4 Level 4 (±2 kV) - withstands burst noise on power and I/O lines in noisy environments |
Pinout & Package
ESD5381MUT5G uses the X3DFN2 (Case 152AF) surface-mount package: 0.60 mm × 0.30 mm body, 0.3 mm height, MSL 1 rated, Pb-free and RoHS compliant. Pin 1 is cathode-marked via laser etch or microdot; Pin 2 is anode.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (Cathode) | Clamping output node | Connected to protected signal line; sinks ESD current to ground when voltage exceeds VRWM |
| Pin 2 (Anode) | Reference terminal | Connected to system ground; completes low-inductance return path for transient current |
Key Features
| Feature | Design Value |
|---|---|
| Low Clamping Voltage | 10.5 V max at 1 A enables protection of 3.3 V logic without overstressing downstream transceivers |
| Ultra-Small Footprint | 0.60 mm × 0.30 mm area reduces PCB real estate use by >50% vs. SOD-323 packages |
| Sub-12 pF Capacitance | Minimizes insertion loss and group delay on high-speed differential pairs (e.g., USB D+/D−) |
| Fast Response Time | <1 ns activation ensures clamping occurs before ESD pulse front reaches protected IC input |
| IEC 61000−4−2/−4−4 Compliance | Validated performance eliminates need for external test validation in end-product certification |
Applications
| USB 2.0 Data Lines | MIPI D-PHY Interfaces |
|---|---|
Use Scenario: Protecting D+ and D− pins of USB 2.0 transceivers in smartphones and tablets against user-hand ESD events. IC Role / Device Role / Timing Role: Unidirectional clamping diode placed between signal line and ground, activated only during positive transients on D+ or negative transients on D−. Use Value: 10.5 V clamping prevents latch-up or gate oxide damage in USB PHY while 12 pF capacitance maintains eye diagram integrity at 480 Mbps. | Use Scenario: Shielding MIPI D-PHY clock and data lanes in camera modules from ESD coupling during board handling or connector mating. IC Role / Device Role / Timing Role: Signal-line ESD suppressor with cathode tied to signal and anode to ground, providing fast turn-on for both polarities via layout symmetry. Use Value: Sub-1 ns response captures ESD energy before it propagates across flex cables, and 0.3 mm profile fits beneath compact camera module connectors. |
| HDMI CEC Channel | Touchscreen I²C Bus |
Use Scenario: Safeguarding HDMI CEC (Consumer Electronics Control) line in TVs and set-top boxes from installation-related ESD. IC Role / Device Role / Timing Role: Low-capacitance unidirectional protector on open-drain CEC bus, referenced to system ground. Use Value: 3.0 V VRWM aligns with CEC logic-high threshold; 100 nA leakage avoids false triggering during idle bus states. | Use Scenario: Protecting I²C SDA/SCL lines connecting capacitive touchscreen controllers to host processors in handheld devices. IC Role / Device Role / Timing Role: Bidirectional protection achieved using two ESD5381MUT5G devices back-to-back per line (anode-to-anode), enabling clamping for both polarities. Use Value: Dual-diode configuration delivers symmetrical ±8 kV protection while maintaining <25 pF total capacitance-within I²C 400 kHz timing budget. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5382MUT5G | Higher clamping voltage (26.0 V max @ 1 A), same VRWM (3.0 V), lower leakage (50 nA), higher breakdown (14.2 V min) | Designed for higher-energy surge paths (e.g., power rails); less suitable for high-speed signal lines due to higher VC | Select ESD5382MUT5G only when protecting 3.3 V supplies or non-critical GPIOs where clamping voltage margin >20 V is acceptable |
| TPD2E001DRYR | Bi-directional configuration, 11.5 V clamping @ 1 A, 12 pF capacitance, same X2SON package (0.8 mm × 0.8 mm) | Requires no anode/cathode orientation planning; larger footprint but easier layout for bidirectional signals like USB or HDMI | Choose TPD2E001DRYR when simplifying layout for bidirectional buses or when footprint tolerance allows 0.8 mm × 0.8 mm |
Compared with ESD5381MUT5G, ESD5382MUT5G trades lower clamping for higher surge robustness-making it better for power-rail protection-while TPD2E001DRYR offers bidirectional operation in a larger but orientation-agnostic package, easing design for mixed-signal interfaces.
Availability
ESD5381MUT5G is available at Aetrix Electronics and suitable for USB 2.0 interface protection, MIPI D-PHY camera modules, and touchscreen I²C bus shielding requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for ESD5381MUT5G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient technologies for automotive, industrial, cloud, medical, and portable electronics.
The ESD5381 Series is part of onsemi's micro-packaged ESD protection portfolio, engineered specifically for ultra-compact, high-speed signal line protection in mobile and wearable devices where board space and signal fidelity are critical constraints.
FAQ
What is the clamping voltage specification for ESD5381MUT5G?
The ESD5381MUT5G has a maximum clamping voltage of 10.5 V at 1 A peak pulse current per IEC 61000−4−2 waveform. This value is measured across the device during an 8 kV contact ESD event and reflects the peak voltage seen by the protected circuit. The low clamping level ensures safe operation of 3.3 V logic interfaces without risking damage to downstream ICs. ESD5381MUT5G consistently achieves this performance under standard test conditions defined in the official datasheet.
Is ESD5381MUT5G unidirectional or bidirectional?
ESD5381MUT5G is a unidirectional ESD protection diode, with cathode (Pin 1) connected to the signal line and anode (Pin 2) tied to ground. It conducts only during positive transients on the signal line relative to ground. For bidirectional protection, two ESD5381MUT5G devices can be placed anode-to-anode or cathode-to-cathode. The device marking and pinout confirm its unidirectional polarity, and this behavior is verified in Figures 1–2 of the ESD5381/D datasheet.
What package type does ESD5381MUT5G use, and what are its dimensions?
ESD5381MUT5G uses the X3DFN2 package (Case 152AF), measuring 0.60 mm × 0.30 mm in footprint and 0.3 mm in height. It complies with MSL 1 moisture sensitivity and supports lead-free reflow up to 260°C. The small size enables placement directly at connector entrances or IC pads in dense portable layouts. Package details-including pin 1 cathode identification and tape-and-reel orientation-are documented in the mechanical drawings of the ESD5381/D datasheet.
Does ESD5381MUT5G meet IEC 61000−4−2 Level 4 ESD immunity?
Yes, ESD5381MUT5G is rated for IEC 61000−4−2 Level 4 ESD immunity: ±8 kV contact discharge and ±15 kV air discharge. This rating is confirmed in the Maximum Ratings table and validated through oscilloscope screenshots in Figures 1 and 2 of the ESD5381/D datasheet. The device's <1 ns response time and low clamping voltage ensure reliable pass/fail performance in end-equipment certification testing.
What is the maximum leakage current of ESD5381MUT5G at its working voltage?
The maximum reverse leakage current for ESD5381MUT5G is 100 nA at its working peak reverse voltage of 3.0 V, measured at TA = 25°C. This low leakage prevents signal degradation or false triggering on high-impedance nodes such as analog sensor inputs or I²C bus lines. The value is specified in the Electrical Characteristics table of the ESD5381/D datasheet and remains stable across temperature ranges from −55°C to +150°C.
ESD5381MUT5G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 0201 (0603 Metric)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Zener
- Unidirectional Channels:
- 1
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3V (Max)
- Voltage - Breakdown (Min):
- 6.1V
- Voltage - Clamping (Max) @ Ipp:
- 10.5V
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 2-X3DFN (0.6x0.3) (0201)
ESD5381MUT5G FAQ
1.How can I place an order for ESD5381MUT5G through Aetrix?
Please submit a Request for Quotation (RFQ) for ESD5381MUT5G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ESD5381MUT5G reliable?
The price and inventory of ESD5381MUT5G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ESD5381MUT5G is usually 5 days.
3.What payment methods are accepted for ESD5381MUT5G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ESD5381MUT5G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ESD5381MUT5G?
ESD5381MUT5G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ESD5381MUT5G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ESD5381MUT5G?
For technical support, including ESD5381MUT5G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ESD5381MUT5G requirements.
6.How does Aetrix verify that ESD5381MUT5G is sourced from the original manufacturer or authorized distributors?
All ESD5381MUT5G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ESD5381MUT5G meets industry standards.
7.What is the process for return or replacement of ESD5381MUT5G?
All ESD5381MUT5G units undergo pre-shipment inspection (PSI). If there is an issue with ESD5381MUT5G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ESD5381MUT5G part is unused and in its original packaging.
Return procedure for ESD5381MUT5G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ESD5381MUT5G Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

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D5V0H1B2LP-7B
Diodes Incorporated

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D5V0P1B2LP-7B
Diodes Incorporated

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DESD5V0U1BA-7
Diodes Incorporated

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ESD5Z5.0T1G
onsemi

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DESD5V0U1BB-7
Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
Nexperia USA Inc.

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DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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