Infineon Technologies GS-065-030-6-LL-MR

Overview

GS-065-030-6-LL from Infineon Technologies is a 700 V enhancement-mode GaN-on-silicon power transistor in TOLL package, delivering R_DS(on) = 40 mΩ, I_DS,max = 40 A (T_case = 25 °C), and 850 V transient drain-to-source voltage. It enables high-efficiency, >1 MHz switching in bridgeless totem-pole PFC stages and datacenter power supplies.

For engineers reviewing the GS-065-030-6-LL datasheet, GS-065-030-6-LL pinout, GS-065-030-6-LL application, or GS-065-030-6-LL equivalent, key selection criteria include bottom-cooled thermal performance (R_θJC = 0.46 °C/W), zero reverse recovery charge (Q_RR = 0 nC), gate drive tolerance (−20 V / +10 V transient), and source sense (SS) pin for optimized gate loop control.

Technical Context

This GaN HEMT uses patented Island Technology® cell layout to achieve high-current die density and yield. Its E-mode operation requires only 0–6 V gate drive, with V_GS(th) = 1.1–2.6 V and internal R_G = 1.3 Ω, enabling direct interfacing with standard logic-level drivers without level-shifting.

The device features a dedicated Source Sense (SS) terminal to eliminate source inductance impact on gate control, ensuring stable high-frequency switching. With Q_GD = 2.3 nC and Q_OSS = 66 nC at V_DS = 400 V, it supports fast, low-loss transitions and minimal turn-off energy (E_off = 10 µJ).

Key Specifications

Pinout & Package

TOLL (Thin Outline Leadless) package with bottom-side thermal pad for direct heatsink attachment; 8 mm × 8 mm footprint, 0.85 mm height, RoHS 3 (6+4) compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar GaN power transistor applications.

Compared with TPH3205WS, GS-065-030-6-LL delivers 5× lower Q_GD, zero Q_RR, and 10× higher frequency capability-making it indispensable for >300 kHz totem-pole PFC. Against GS-065-011-1-L-MR, it trades 2.7× higher R_DS(on) for 30% smaller footprint and lower gate drive power.

Availability

GS-065-030-6-LL is available at Aetrix Electronics and suitable for bridgeless totem-pole PFC, industrial high-density SMPS, and solar string inverter designs requiring stable component supply, long-term lifecycle support, and qualified GaN reliability data.

Supply support for GS-065-030-6-LL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor leader specializing in power, sensor, and automotive ICs, with global manufacturing and R&D infrastructure supporting industrial and energy-efficient applications.

This device belongs to Infineon's GaN Systems portfolio of enhancement-mode GaN transistors, engineered specifically for high-frequency, high-efficiency AC-DC and DC-DC conversion in datacenter, renewable energy, and industrial power systems.

FAQ

What gate driver is recommended for GS-065-030-6-LL?

Infineon recommends gate drivers with 0–6 V output swing, peak sink/source current ≥2 A, and integrated negative voltage capability (e.g., 1EDN7512B). The SS pin must be routed separately to the driver's source reference to maintain low-inductance gate loop integrity and prevent oscillation during >1 MHz switching.

Can GS-065-030-6-LL replace silicon MOSFETs in existing designs?

Yes-but only with layout revision: the SS pin requires dedicated Kelvin routing, the TOLL package needs optimized thermal vias under the bottom pad (0.3 mm diameter, 0.635 mm pitch), and gate drive traces must be shortened to ≤5 mm to avoid ringing due to its 5.7 ns fall time and low Q_GD.

Does GS-065-030-6-LL support reverse conduction in synchronous rectification?

Yes-it exhibits controlled reverse conduction with V_SD ≈ 1.8 V at 20 A and no reverse recovery charge. This enables true synchronous rectification in LLC and phase-shifted full-bridge topologies without body diode loss or shoot-through risk, provided gate timing accounts for its ~15 ns reverse turn-on delay.

What is the maximum allowable PCB copper thickness for thermal vias under the TOLL pad?

The datasheet specifies 2 oz. (70 µm) copper per layer for the 4-layer FR4 board used in R_θJA characterization. Thicker copper (e.g., 3 oz.) is permissible but requires revalidation of thermal via fill quality and aspect ratio (≤3:1) to avoid voiding; insufficient plating increases R_θJC by up to 15%.