Nexperia USA Inc. IP4369CX4YL
- Part No.:
- IP4369CX4YL
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- 4-XFBGA, WLCSP
- Datasheet:
-
IP4369CX4YL.pdf
- Description:
- TVS DIODE 5.5VWM 4VC 4WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:8,700
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Product details
Overview
IP4369CX4YL from Nexperia is a 4-channel ESD protection diode array in WLCSP4 package, designed for high-speed differential interfaces including HDMI, USB 2.0 (480 Mbit/s), DisplayPort, eSATA, and LVDS. It delivers ±8 kV IEC 61000-4-2 contact ESD protection with ultra-low 0.8 pF typical line capacitance per channel and 0.4 pF inter-channel capacitance, enabling signal integrity preservation in mobile handset and portable device port protection.
For engineers reviewing the IP4369CX4YL datasheet, IP4369CX4YL pinout, IP4369CX4YL application, or IP4369CX4YL equivalent, key selection criteria include sub-1 pF capacitance, rail-to-rail clamping architecture, 2×2 WLCSP footprint (<500 µm height), and verified USB 2.0 eye diagram performance with minimal distortion.
Technical Context
This device implements a snap-back clamping structure with negative dynamic resistance-0.24 Ω (positive transient) and 0.21 Ω (negative transient)-to suppress clamping voltage to +4 V / −3 V at 4–5 A surge current per IEC 61000-4-5. Its low capacitance matching (≤0.05 pF between signal pairs) ensures minimal skew in differential signaling paths.
The integrated rail-to-rail diode configuration protects both signal lines and ground reference simultaneously, supporting bidirectional ESD transients without external biasing. All four terminals are configured as two protected channels (A1/A2 signal pair, B1/B2 ground return), validated for operation across −30 °C to +85 °C ambient.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±8 kV contact discharge per IEC 61000-4-2 Level 4 - ensures robust system-level immunity in handheld device ports |
| Line Capacitance | 0.8 pF typical per channel at 1 MHz - preserves signal integrity up to USB 2.0 high-speed (480 Mbit/s) |
| Inter-Pair Capacitance | 0.4 pF typical - minimizes crosstalk-induced jitter in differential interfaces like HDMI and LVDS |
| Clamping Voltage | +4 V at +4 A / −3 V at −5 A per IEC 61000-4-5 - limits downstream IC stress during surge events |
| Dynamic Resistance | 0.21–0.24 Ω (TLP, 100 ns) - enables rapid voltage collapse during ESD snap-back for effective protection |
| Package Dimensions | 0.76 mm × 0.76 mm × <0.5 mm WLCSP4 (2×2 bumps, 0.4 mm pitch) - supports ultra-dense PCB layouts in smartphones |
| Operating Temperature | −30 °C to +85 °C - qualified for consumer portable electronics thermal environments |
Pinout & Package
IP4369CX4YL uses a 2×2 Wafer-Level Chip-Scale Package (WLCSP4) with solder bumps on bottom side; total height <500 µm. Index area marked at A1 corner. Package outline conforms to Nexperia WLCSP4 standard (D/E = 0.76 mm typ, e = 0.40 mm pitch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1, A2 | Protected signal lines | Input/output pins for one differential or single-ended high-speed data channel; each features integrated clamping diodes to GND |
| B1, B2 | Ground reference terminals | Dedicated low-inductance ground return path for ESD current; must be connected to solid PCB ground plane via micro-vias |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail clamping architecture | Enables full-swing signal protection without DC biasing, supporting AC-coupled interfaces like HDMI and USB |
| 0.05 pF max capacitance matching | Maintains phase alignment between differential pairs, critical for LVDS and DisplayPort timing margins |
| SnAgCu Pb-free solder compatibility | Withstands ≥3 reflow cycles up to 260 °C peak, compliant with IPC-J-STD-020 moisture sensitivity level 1 |
| NSMD PCB pad recommendation | Specifies 250 µm copper pads with 100 µm laser micro-vias to minimize ground loop inductance below 0.3 nH |
| Ultra-thin profile | Height <500 µm allows integration beneath display modules or under battery compartments in slim mobile designs |
Applications
| USB 2.0 High-Speed Port Protection | HDMI Interface Receiver Protection |
|---|---|
|
Use Scenario: Protecting micro-USB receptacles in smartphones against user-handling ESD during cable insertion/removal. IC Role / Device Role / Timing Role: Bidirectional ESD clamp placed directly at connector, before USB PHY transceiver. Use Value: Maintains 480 Mbit/s eye diagram integrity (Fig 7) while suppressing ±8 kV transients to <±4 V clamping level. |
Use Scenario: Shielding HDMI Type-D (micro-HDMI) ports in tablets from ESD during docking/undocking. IC Role / Device Role / Timing Role: Differential pair protector on TMDS clock/data lanes, referenced to local ground plane. Use Value: 0.4 pF inter-pair capacitance prevents skew-induced jitter; 0.8 pF per-line capacitance avoids bandwidth roll-off above 1 GHz. |
| eSATA Connector Protection | LVDS Camera Interface Protection |
|
Use Scenario: Safeguarding external SATA ports in portable SSD enclosures exposed to field ESD events. IC Role / Device Role / Timing Role: Single-ended ESD clamp on TX/RX lines, with dedicated ground return (B1/B2) routed to chassis ground. Use Value: 0.21 Ω dynamic resistance ensures fast clamping response (<1 ns), limiting voltage overshoot during 30 A surge pulses. |
Use Scenario: Securing high-speed MIPI D-PHY camera links in foldable phone hinge zones prone to repeated flex-induced ESD. IC Role / Device Role / Timing Role: Dual-channel protector applied to LP/HS lane pairs, leveraging matched capacitance for common-mode noise rejection. Use Value: ≤0.05 pF capacitance mismatch preserves differential skew budget under 10 ps, meeting MIPI D-PHY v2.1 timing requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD4E001DQAR (TI) | 0.6 pF line capacitance, SOT-5X3 package (1.45 mm × 1.0 mm), higher 1.2 mm height | Preferred for space-constrained but height-tolerant designs; lacks WLCSP miniaturization | Select when board assembly favors SMT placement over WLCSP reflow and ground inductance is less critical |
| ESD56084D05 (ON Semi) | 0.5 pF capacitance, 4-channel WLCSP but 0.5 mm pitch (vs. 0.4 mm), 0.65 mm × 0.65 mm footprint | Suitable for mid-tier portable devices where 0.1 mm pitch reduction is non-essential | Choose when existing PCB stencil supports 0.5 mm pitch and lower capacitance justifies larger die area |
Compared with TPD4E001DQAR and ESD56084D05, IP4369CX4YL offers the smallest footprint (0.76 mm²) and tightest capacitance matching (≤0.05 pF), making it optimal for flagship smartphone front-panel interface protection where board real estate and signal fidelity are paramount.
Availability
IP4369CX4YL is available at Aetrix Electronics and suitable for mobile handset design, USB 2.0 peripheral development, and HDMI-enabled portable displays requiring stable component supply and consistent WLCSP4 sourcing.
Supply support for IP4369CX4YL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-performance, reliable discrete, logic, and MOSFET solutions, with leadership in ESD protection and automotive-grade components.
IP4369CX4YL belongs to Nexperia's high-speed interface ESD protection product line, engineered specifically for miniaturized consumer electronics demanding sub-1 pF capacitance and ±8 kV system-level immunity.
FAQ
What is the maximum recommended PCB trace length between IP4369CX4YL and the protected connector?
Trace length should not exceed 3 mm from device solder bump to connector pin to maintain low-inductance ESD current path. Longer traces increase ground loop inductance, degrading clamping response and risking voltage overshoot beyond the ±4 V/−3 V spec. Use direct micro-via connections to inner ground planes as specified in Nexperia's PCB design guidelines.
Can IP4369CX4YL be used for USB 3.0 or PCIe Gen2 interfaces?
No-IP4369CX4YL is characterized only up to 1 GHz (validated for USB 2.0's 240 MHz fundamental), and its 0.8 pF capacitance causes unacceptable insertion loss above 2 GHz. USB 3.0 and PCIe Gen2 require sub-0.3 pF protectors such as Nexperia's PESD5V0S1BA or TI's TPD6S300A.
Is external decoupling capacitance required at the B1/B2 ground terminals?
No external capacitor is needed or recommended. The device relies on low-inductance PCB ground plane coupling via micro-vias. Adding discrete capacitors introduces parasitic inductance that compromises high-frequency ESD current shunting. Follow Nexperia's NSMD pad and buried ground plane recommendations instead.
Does IP4369CX4YL support hot-plug detection in USB OTG applications?
IP4369CX4YL does not implement any logic or sensing function-it is a passive clamping diode array. Hot-plug detection remains handled by the USB PHY or controller IC. The device only provides ESD robustness during plug/unplug events, with no impact on ID pin detection or VBUS monitoring circuitry.
IP4369CX4YL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- 4-XFBGA, WLCSP
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 4V (Typ)
- Current - Peak Pulse (10/1000µs):
- 4A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.8pF @ 1MHz
- Operating Temperature:
- -35°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 4-WLCSP (0.76x0.76)
IP4369CX4YL FAQ
1.How can I place an order for IP4369CX4YL through Aetrix?
Please submit a Request for Quotation (RFQ) for IP4369CX4YL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for IP4369CX4YL reliable?
The price and inventory of IP4369CX4YL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for IP4369CX4YL is usually 5 days.
3.What payment methods are accepted for IP4369CX4YL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for IP4369CX4YL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for IP4369CX4YL?
IP4369CX4YL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your IP4369CX4YL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for IP4369CX4YL?
For technical support, including IP4369CX4YL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your IP4369CX4YL requirements.
6.How does Aetrix verify that IP4369CX4YL is sourced from the original manufacturer or authorized distributors?
All IP4369CX4YL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that IP4369CX4YL meets industry standards.
7.What is the process for return or replacement of IP4369CX4YL?
All IP4369CX4YL units undergo pre-shipment inspection (PSI). If there is an issue with IP4369CX4YL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The IP4369CX4YL part is unused and in its original packaging.
Return procedure for IP4369CX4YL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
IP4369CX4YL Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

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D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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