Infineon Technologies IPD60R650CEAUMA1

Overview

IPD60R650CEAUMA1 from Infineon Technologies is a 600 V, 9.9 A superjunction N-channel MOSFET in DPAK (PG-TO252) package, featuring R_DS(on) = 650 mΩ max at V_GS = 10 V and Q_g = 20.5 nC typ. It delivers low E_oss (1.9 µJ @ 400 V), high commutation ruggedness, and is optimized for cost-sensitive PFC and hard-switching PWM stages in indoor lighting and adapter power supplies.

For engineers reviewing the IPD60R650CEAUMA1 datasheet, IPD60R650CEAUMA1 pinout, IPD60R650CEAUMA1 application, or IPD60R650CEAUMA1 equivalent, key selection criteria include its 600 V V_DS, 650 mΩ R_DS(on), 20.5 nC gate charge, 1.52 °C/W R_thJC, and DPAK thermal performance under PCB-constrained cooling.

Technical Context

This CoolMOS™ CE device implements superjunction architecture to achieve ultra-low figure-of-merit (R_DS(on) × Q_g) while maintaining robust dv/dt ruggedness (50 V/ns) and reverse diode commutation capability (500 A/µs). Its gate threshold voltage (2.5–3.5 V) ensures stable turn-on with standard 10 V gate drivers.

The MOSFET supports both unidirectional switching and synchronous rectification roles, with validated avalanche energy rating (E_AS = 133 mJ) and reverse recovery parameters (Q_rr = 2.1 µC, t_rr = 250 ns) enabling reliable operation in discontinuous conduction mode (DCM) PFC and resonant topologies.

Key Specifications

Pinout & Package

DPAK (PG-TO252) package with exposed drain pad for thermal enhancement; surface-mount, single-row 3-pin configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage MOSFET applications.

Compared with STP6N60DM6 and FDPF6N60NZ, IPD60R650CEAUMA1 offers superior thermal resistance (1.52 vs. ≥2.0 °C/W), lower gate charge (20.5 vs. ≥25 nC), and documented E_oss-making it optimal for compact, high-efficiency SMT-based power supplies targeting consumer lighting and adapter markets.

Availability

IPD60R650CEAUMA1 is available at Aetrix Electronics and suitable for indoor lighting drivers, AC-DC adapters, and PC silver box power supplies requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for IPD60R650CEAUMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive electronics, and industrial control ICs, with global R&D and wafer fabrication facilities.

This device belongs to the CoolMOS™ CE family-a cost-optimized superjunction MOSFET platform targeting high-efficiency, price-sensitive offline power conversion in consumer and lighting applications.

FAQ

What is the maximum continuous drain current for IPD60R650CEAUMA1 at 100°C case temperature?

The maximum continuous drain current is 6.2 A at T_C = 100°C, as specified in Table 2 of the datasheet. This derating reflects thermal limitations of the DPAK package under realistic board-level cooling conditions, not silicon capability alone.

Does IPD60R650CEAUMA1 support paralleling in high-current designs?

Yes, but with specific layout requirements: ferrite beads must be placed on each gate line, and separate totem-pole drivers are recommended to ensure balanced gate voltage rise/fall times and prevent current imbalance during switching transitions.

Is the drain tab electrically isolated from the PCB in the DPAK package?

No-the drain tab is internally connected to Pin 2 and is electrically active at drain potential. It must be routed on a dedicated high-voltage copper pour with adequate creepage/clearance (≥4 mm) and cannot be grounded or connected to any other net.

What is the safe operating area (SOA) limitation at 80°C case temperature for pulsed operation?

At T_C = 80°C, the SOA curve (Diagram 7) limits single-pulse ID to 4.5 A at V_DS = 400 V for pulse widths up to 100 µs. Beyond that, thermal saturation restricts operation to lower current or shorter pulses to avoid junction overheating.