Infineon Technologies IPDQ60R065S7XTMA1

Overview

IPDQ60R065S7XTMA1 from Infineon is a 600 V, 65 mΩ silicon carbide-free Superjunction MOSFET in CoolMOS™ S7 technology, optimized for static switching and high-current line rectification in industrial SMPS and inverters. It features Kelvin Source (pin 2), integrated body diode, 126 A pulsed drain current, and QDPAK (PG-HDSOP-22-1) package with top-side cooling.

For engineers reviewing the IPDQ60R065S7XTMA1 datasheet, IPDQ60R065S7XTMA1 pinout, IPDQ60R065S7XTMA1 application, or IPDQ60R065S7XTMA1 equivalent, key selection criteria include R_DS(on) stability at 150°C, dv/dt ruggedness (20 V/ns), internal Kelvin Source implementation, and thermal resistance (R_thJC = 0.64 °C/W) for solid-state relay and circuit breaker designs.

Technical Context

This device implements Infineon's 7th-generation CoolMOS™ SJ architecture with charge compensation trench structure, delivering lowest R_DS(on) per die area among 600 V HV SJ MOSFETs. Its gate threshold voltage (3.5–4.5 V) and plateau voltage (5.4 V) support robust TTL/CMOS-level drive compatibility.

The Kelvin Source configuration (pin 2) separates driver return path from power source (pins 3–11), enabling precise gate control under high di/dt conditions. The internal body diode exhibits 0.82 V forward drop at 8 A and 310 ns reverse recovery time - critical for hard-switched PFC and inverter freewheeling paths.

Key Specifications

Pinout & Package

Package: PG-HDSOP-22-1 (QDPAK), thermally enhanced surface-mount with exposed copper tab for top-side cooling. Dimensions: 15.8 × 10.1 × 4.5 mm (L × W × H). Tab is electrically connected to Drain (pins 12–22).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage static switching applications.

Compared with IPW60R075CFD7 and IPP60R099C7, IPDQ60R065S7XTMA1 delivers superior thermal performance (0.64 °C/W vs. ≥1.2 °C/W), Kelvin Source integrity for high-current stability, and 12% lower R_DS(on) - making it the only option qualified for 126 A pulsed operation in compact QDPAK form factor.

Availability

IPDQ60R065S7XTMA1 is available at Aetrix Electronics and suitable for solid-state relays, industrial UPS inverters, and solar string inverters requiring stable component supply, JEDEC-qualified industrial reliability, and long-term lifecycle continuity.

Supply support for IPDQ60R065S7XTMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power semiconductors, microcontrollers, and sensor solutions for industrial, automotive, and energy markets.

This device belongs to the CoolMOS™ S7 Superjunction MOSFET product line, engineered specifically for static switching, high-current rectification, and low-frequency (<100 kHz) power conversion where conduction loss dominates system efficiency.

FAQ

Can IPDQ60R065S7XTMA1 be paralleled with identical units?

Yes, but gate resistors must be placed on the Driver Source (pin 2), not the Gate (pin 1), to ensure balanced current sharing. The Kelvin Source pin prevents gate loop inductance from causing dynamic imbalance. Parallel operation requires matched layout symmetry and identical thermal mounting of all devices' tabs to avoid thermal runaway.

What is the maximum allowable gate-source voltage during transient conditions?

The absolute maximum dynamic gate-source voltage is ±30 V (AC, f > 1 Hz). Exceeding this risks oxide breakdown. During fast switching, overshoot must be clamped using Zener diodes or active gate control - especially when driving inductive loads where ringing can exceed 25 V peak-to-peak.

Is the internal body diode suitable for synchronous rectification?

No. The body diode has 310 ns reverse recovery time and 3.9 µC Q_rr, making it unsuitable for high-frequency synchronous rectification (>50 kHz). It is designed for low-frequency freewheeling and line rectification where recovery loss is secondary to conduction loss.

How does the PG-HDSOP-22-1 package affect PCB layout requirements?

The exposed drain tab requires full isolation from the PCB ground plane using insulating thermal pads or ceramic substrates. Minimum creepage distance from tab edges to nearest conductor must be ≥4.5 mm for 600 V working voltage. Thermal vias under the tab are prohibited - heat flows vertically through the tab to the heatsink, not into the board.