Infineon Technologies IPL60R210P6AUMA1

Overview

IPL60R210P6AUMA1 from Infineon Technologies is a 600 V, 210 mΩ superjunction MOSFET in ThinPAK 8x8 package with drain-connected pin 5, gate on pin 1, and dual-source configuration (pins 2, 3, 4). It delivers 19.2 A continuous drain current at 25°C, 37 nC total gate charge, and 4.9 µJ output switching energy at 400 V - optimized for high-efficiency PFC and hard-switching SMPS in server power supplies and telecom rectifiers.

For engineers reviewing the IPL60R210P6AUMA1 datasheet, IPL60R210P6AUMA1 pinout, IPL60R210P6AUMA1 application, or IPL60R210P6AUMA1 equivalent, key selection criteria include R_DS(on) vs. temperature stability, dv/dt ruggedness (100 V/ns), diode commutation speed (500 A/µs), and thermal resistance (0.83 °C/W junction-to-case).

Technical Context

This CoolMOS™ P6 device implements a charge-balanced superjunction structure enabling low R_DS(on) × Q_g figure-of-merit (210 mΩ × 37 nC) and ultra-low E_oss (4.9 µJ at 400 V). Its gate plateau voltage is 6.1 V, and it supports 13 V gate drive with 3.4 Ω internal gate resistance.

The integrated body diode exhibits 0.9 V forward voltage at 9.5 A and 310 ns reverse recovery time under 100 A/µs diF/dt stress. Thermal design is enabled by 0.83 °C/W R_thJC, allowing high-power density layouts on minimal copper footprints.

Key Specifications

Pinout & Package

Package: ThinPAK 8x8 (PG-VSON-4), surface-mount, exposed drain pad for thermal enhancement. Pin 1 = Gate, Pin 2 = Source (Driver), Pins 3–4 = Source (Power), Pin 5 = Drain.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage superjunction MOSFET applications.

Compared with STP60N6F6 and IXTH50N60L2, IPL60R210P6AUMA1 delivers lowest R_DS(on) × Q_g FOM and highest diF/dt rating - making it optimal for compact, high-frequency, high-reliability PFC and resonant converters where thermal headroom and EMI control are critical.

Availability

IPL60R210P6AUMA1 is available at Aetrix Electronics and suitable for server power supplies, telecom rectifiers, LCD TV backlight inverters, and UPS inverter stages requiring stable component supply, JEDEC-qualified industrial reliability, and consistent parametric performance across production lots.

Supply support for IPL60R210P6AUMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs and discrete devices, with global manufacturing and R&D infrastructure.

The CoolMOS™ P6 series was engineered specifically for high-efficiency, high-power-density AC-DC conversion - targeting next-generation server PSUs, telecom infrastructure, and industrial SMPS where reduced conduction loss, enhanced ruggedness, and simplified drive requirements are mandatory.

FAQ

What is the maximum continuous drain current for IPL60R210P6AUMA1 at 100°C case temperature?

The maximum continuous drain current is 12.1 A at T_C = 100°C, as specified in Table 2 of the Rev. 2.1 datasheet. This value is thermally limited by the 150°C maximum junction temperature and 0.83 °C/W junction-to-case thermal resistance - not by package current rating alone.

Does IPL60R210P6AUMA1 require a negative gate voltage for reliable turn-off?

No. The device is fully characterized for 0 V to +13 V gate drive, with no requirement for negative bias. Its gate threshold voltage (3.5–4.5 V) and 30 V dynamic gate-source rating allow robust operation using standard unipolar gate drivers without level-shifting or negative rail generation.

Can IPL60R210P6AUMA1 replace older CoolMOS™ P5 devices in existing designs?

Yes - it is a direct drop-in replacement for IPL60R210P5 in most cases. Key improvements include 15% lower E_oss, 10% higher dv/dt ruggedness, and tighter R_DS(on) distribution. Layout and gate drive remain unchanged, but efficiency gains of 0.3–0.5% are typical in PFC stages.

What is the recommended PCB layout for thermal performance in ThinPAK 8x8?

Infineon specifies a 40 mm × 40 mm × 1.5 mm FR4 board with 6 cm² of 70 µm-thick copper connected to the exposed drain pad (Pin 5). No thermal vias are required, but 8–12 thermal vias (0.3 mm diameter, 0.8 mm pitch) beneath the pad further reduce R_thJA to ≤35 °C/W in forced-air conditions.