Infineon Technologies IPL65R099C7AUMA1

Overview

IPL65R099C7AUMA1 from Infineon Technologies is a 650 V, 99 mΩ superjunction N-channel MOSFET in ThinPAK 8x8 package, featuring driver source pin (Pin 2), gate pin (Pin 1), and dual power source pins (Pins 3 & 4). It delivers 21 A continuous drain current at T_C = 25°C, 45 nC total gate charge, and 5.5 µJ E_oss at 400 V - optimized for high-efficiency PFC and hard-switching PWM stages in server PSUs and telecom rectifiers.

For engineers reviewing the IPL65R099C7AUMA1 datasheet, IPL65R099C7AUMA1 pinout, IPL65R099C7AUMA1 application, or IPL65R099C7AUMA1 equivalent, key selection criteria include R_DS(on) × Q_g figure-of-merit, dv/dt ruggedness (100 V/ns), diode dI_F/dt capability (60 A/µs), and thermal resistance (R_thJC = 0.98 °C/W) for high-power-density designs.

Technical Context

This CoolMOS™ C7 device implements a superjunction architecture with optimized charge balancing for reduced conduction and switching losses. Its driver source pin enables precise gate control by separating gate return path from power source return, minimizing common-source inductance and improving switching stability under high di/dt conditions.

The MOSFET supports industrial-grade operation up to T_j = 150°C and exhibits robust avalanche capability (E_AS = 118 mJ) and reverse diode commutation performance (trr = 700 ns, Q_rr = 8 µC), making it suitable for discontinuous and continuous conduction mode topologies without external snubbers in many cases.

Key Specifications

Pinout & Package

Package: ThinPAK 8x8 (PG-VSON-4), surface-mount, leadless, with exposed drain pad for low-inductance thermal path and enhanced power density.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage superjunction MOSFET applications.

Compared with IPW65R099C7 and STP65N9F6, IPL65R099C7AUMA1 provides superior power density via ThinPAK packaging, lower system-level EMI through driver source isolation, and verified 100 V/ns dv/dt immunity - essential for next-generation 1U server and 5G telecom power systems.

Availability

IPL65R099C7AUMA1 is available at Aetrix Electronics and suitable for server power supply PFC stages, telecom rectifier modules, solar inverter DC-DC converters, and UPS inverter half-bridges requiring stable component supply and long-term industrial lifecycle support.

Supply support for IPL65R099C7AUMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs and discrete devices, with global manufacturing and quality certification to ISO/TS 16949 and IECQ QC 080000.

The CoolMOS™ C7 series targets high-efficiency, high-power-density AC-DC conversion in datacenter, telecom, and renewable energy systems, emphasizing reduced switching loss, improved ruggedness, and simplified gate drive implementation.

FAQ

What is the maximum recommended gate resistor value for IPL65R099C7AUMA1 in a 100 kHz PFC application?

The datasheet specifies 5.3 Ω gate resistor for characterization at 400 V and 5.9 A. For 100 kHz PFC, a 10–15 Ω resistor balances switching loss reduction and EMI control while maintaining safe dv/dt margins. Lower values increase peak gate current and risk oscillation; higher values extend fall time beyond 12 ns, raising turn-off loss.

Does IPL65R099C7AUMA1 require a gate resistor between gate and driver source pin?

No - the driver source pin (Pin 2) is intended as the dedicated return path for the gate driver's low-side output. A gate resistor is placed between driver output and Pin 1 (gate); Pin 2 connects directly to the driver's ground reference to minimize loop inductance and suppress Miller feedback.

Can IPL65R099C7AUMA1 be paralleled with identical units without external gate ferrite beads?

No - the datasheet explicitly recommends ferrite beads on each gate or separate totem-pole drivers for paralleling. Without them, mismatched propagation delays and stray inductance cause current imbalance and thermal runaway, especially above 15 A per device in hard-switching configurations.

What is the minimum PCB copper area required for thermal performance at 128 W power dissipation?

Per Table 3, the specified R_thJA of 35–45 °C/W assumes a 40 mm × 40 mm × 1.5 mm FR4 PCB with 6 cm² of 70 µm-thick copper on one layer connected to the drain pad. For 128 W at T_C = 25°C, this yields ~45–58°C junction rise - confirming the 6 cm² area is the validated minimum for rated power under vertical natural convection.