Infineon Technologies IPL65R130C7AUMA1

Overview

IPL65R130C7AUMA1 from Infineon Technologies is a 650 V, 130 mΩ superjunction MOSFET in the CoolMOS™ C7 family, designed for high-efficiency hard-switching and PFC stages. It delivers typ. Qg = 35 nC, Eoss = 4.2 µJ at 400 V, and features a driver source pin (Pin 2) for improved gate control in high-frequency power converters used in telecom rectifiers and server PSUs.

For engineers reviewing the IPL65R130C7AUMA1 datasheet, IPL65R130C7AUMA1 pinout, IPL65R130C7AUMA1 application, or IPL65R130C7AUMA1 equivalent, key selection criteria include RDS(on)×Eoss figure-of-merit, dv/dt ruggedness (100 V/ns), diF/dt capability (55 A/µs), and ThinPAK 8x8 SMD package thermal performance.

Technical Context

This 650 V CoolMOS™ C7 device implements a charge-compensated superjunction structure enabling lower conduction and switching losses than previous generations. Its optimized cell design reduces Qg by ~25% versus C6 while maintaining robust avalanche rating (EAS = 89 mJ) and high diF/dt (55 A/µs) for fast body diode commutation in continuous conduction mode PFC.

The ThinPAK 8x8 package integrates a dedicated driver source pin (Pin 2) to minimize common-source inductance during turn-on/off transients, and uses drain-connected pins (Pin 5) to reduce loop inductance-critical for >100 kHz operation in compact 1U server PSUs and solar inverters.

Key Specifications

Pinout & Package

Package: ThinPAK 8x8 (PG-VSON-4), surface-mount, leadless, with exposed drain pad for thermal conduction and low-inductance layout.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage superjunction MOSFET applications.

Compared with IPL65R130C7AUMA1, IPW65R095C7 trades higher switching loss for lower conduction loss, while STP65N10F7 sacrifices SMD thermal performance and gate control precision for legacy through-hole compatibility and lower unit cost.

Availability

IPL65R130C7AUMA1 is available at Aetrix Electronics and suitable for telecom rectifiers, server PSU PFC stages, solar inverter DC-link switches, and UPS inverter half-bridges requiring stable component supply and industrial-grade reliability.

Supply support for IPL65R130C7AUMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive, and industrial control ICs and discrete devices, with global manufacturing and R&D infrastructure.

The CoolMOS™ C7 series targets high-efficiency, high-power-density AC-DC and DC-DC conversion in computing, telecom, and renewable energy systems-emphasizing reduced switching loss, enhanced ruggedness, and ease of gate drive implementation.

FAQ

What is the maximum recommended gate resistor value for IPL65R130C7AUMA1 in a 100 kHz PFC application?

The datasheet specifies typical turn-on delay (11 ns) and fall time (12 ns) with RG = 10 Ω. For 100 kHz operation with soft switching, RG ≤ 15 Ω maintains acceptable switching speed while limiting peak gate current to <2 A with a 13 V driver. Higher values increase switching loss and risk incomplete turn-on at high temperature due to V_GS(th) drift.

Does IPL65R130C7AUMA1 require external gate resistors for paralleling, and why?

Yes-Infineon recommends individual gate resistors (and optionally ferrite beads) for each paralleled device to balance dynamic current sharing. Without them, mismatched gate loop inductance causes unequal turn-on timing, leading to current hogging and thermal runaway. The driver source pin helps but does not eliminate need for per-device RG.

How does the driver source pin (Pin 2) improve switching behavior compared to standard 3-pin SMD MOSFETs?

Pin 2 provides a dedicated Kelvin connection to the source region, separating high-current source return (Pins 3/4) from gate drive reference. This eliminates voltage drop across source bond wires/leads during di/dt transients, preventing gate-to-source voltage collapse and ensuring accurate gate threshold control during hard switching.

Can IPL65R130C7AUMA1 be used in zero-voltage switching (ZVS) resonant topologies without derating?

Yes-the 100 V/ns dv/dt ruggedness and 89 mJ single-pulse avalanche rating allow safe operation in LLC and phase-shifted full-bridge topologies. However, R_DS(on) increases with temperature (0.30 Ω at 150°C), so thermal design must ensure T_j stays ≤135°C under peak ZVS conditions to maintain conduction margin.