Infineon Technologies IPS105N03LGAKMA1

Overview

IPS105N03LGAKMA1 from Infineon Technologies is a N-channel enhancement-mode MOSFET rated for 30 V V_DS, 35 A continuous drain current at T_C = 25 °C, and 1.8 mΩ typical R_DS(on) at V_GS = 10 V. It features OptiMOS™ 3 technology, TO-251-3 (IPAK) package, and is designed for high-efficiency DC-DC power stages in server VRMs and POL converters.

For engineers reviewing the IPS105N03LGAKMA1 datasheet, IPS105N03LGAKMA1 pinout, IPS105N03LGAKMA1 application, or IPS105N03LGAKMA1 equivalent, key selection criteria include R_DS(on) vs. gate charge trade-off, thermal resistance (R_thJC = 1.4 K/W), avalanche ruggedness rating, and SOA compliance under synchronous rectification conditions.

Technical Context

This MOSFET employs trench-gate silicon process with optimized cell pitch and reduced specific on-resistance. Its gate threshold voltage (V_GS(th)) ranges from 1.0 V to 2.2 V, enabling compatibility with 3.3 V and 5 V gate drivers. The device supports 100% UIS-rated avalanche energy of 110 mJ at T_J = 25 °C.

Thermal design is enabled by low junction-to-case thermal resistance (1.4 K/W) and a copper clip construction that minimizes parasitic inductance. The TO-251-3 package uses standard through-hole mounting with isolated drain tab for PCB-level heat sinking.

Key Specifications

Pinout & Package

IPS105N03LGAKMA1 is housed in a TO-251-3 (IPAK) package with gull-wing leads and an exposed drain pad on the underside. The package provides mechanical robustness for automated through-hole assembly and thermal path to PCB copper.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar N-channel power MOSFET applications.

Compared with STP35NF3L and IRF7470PBF, IPS105N03LGAKMA1 delivers the lowest R_DS(on) in TO-251-3 form factor while maintaining avalanche robustness and thermal performance required for high-density server power stages.

Availability

IPS105N03LGAKMA1 is available at Aetrix Electronics and suitable for server VRMs, industrial motor drives, telecom power supplies, and automotive body control modules requiring stable component supply and long-term production continuity.

Supply support for IPS105N03LGAKMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive electronics, and security solutions, with global manufacturing and R&D infrastructure.

This part belongs to the OptiMOS™ 3 family, engineered specifically for high-efficiency, high-current DC-DC conversion in datacenter, telecom, and industrial power systems.

FAQ

What is the maximum pulsed drain current rating for IPS105N03LGAKMA1?

The datasheet specifies I_DM = 140 A as the absolute maximum pulsed drain current, defined for pulse width ≤ 10 µs and duty cycle ≤ 1%. This rating assumes case temperature remains below 25 °C and accounts for transient thermal limits during short-circuit events in synchronous buck topologies.

Does IPS105N03LGAKMA1 support gate drive from a 3.3 V microcontroller?

Yes - its gate threshold voltage V_GS(th) is specified from 1.0 V to 2.2 V, and it achieves R_DS(on) ≤ 3.5 mΩ at V_GS = 4.5 V. A 3.3 V GPIO can reliably turn it on in low-speed switching applications, though full 10 V drive is recommended for minimum conduction loss in high-frequency VRMs.

Is the drain tab of IPS105N03LGAKMA1 electrically isolated?

No - the exposed drain pad on the TO-251-3 package is electrically connected to Pin 3 (Drain). It must be mounted on a non-isolated copper area or heatsink tied to the drain net. Electrical isolation requires external insulating hardware or use of a different package variant.

What is the recommended PCB layout for thermal performance?

Designers should use ≥ 4 cm² of 2-oz copper connected directly to the drain pad via ≥ 8 thermal vias (0.3 mm diameter, filled or capped). Keep gate traces short and shielded from drain switching noise. Maintain ≥ 0.5 mm clearance between source and gate pads to prevent coupling during fast dV/dt transitions.