Microchip Technology JAN1N6143US/TR
- Part No.:
- JAN1N6143US/TR
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- SQ-MELF, C
- Datasheet:
-
JAN1N6143US/TR.pdf
- Description:
- BI-DIRECTIONAL TVS
- Quantity:
- Payment:

- Shipping:

Inventory:4,497
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Product details
Overview
JAN1N6143US/TR from Microsemi is a military-qualified, voidless hermetically sealed bidirectional Transient Voltage Suppressor (TVS) in SQ-MELF package, rated for 1500 W peak pulse power (10/1000 µs), 8.4 V working standoff voltage (VWM), and 15.6 V clamping voltage (VC) at 96.2 A peak pulse current - deployed in avionics power bus protection and radar front-end ESD hardening.
For engineers reviewing the JAN1N6143US/TR datasheet, JAN1N6143US/TR pinout, JAN1N6143US/TR application, or JAN1N6143US/TR equivalent, this part delivers MIL-PRF-19500/516 qualified transient suppression with Category 1 metallurgical bonds, triple-layer passivation, and -55°C to +175°C junction temperature operation - critical for high-reliability defense electronics design and radiation-hardened subsystems.
Technical Context
This TVS operates bidirectionally without polarity marking and uses hard-glass construction with tungsten slugs for thermal stability. Its breakdown voltage is 10.45 V at 125 mA test current, with a low 0.07 %/°C temperature coefficient of V(BR), enabling stable clamping across wide ambient ranges.
The device achieves 1500 W peak pulse power handling via low dynamic impedance during surge events, supported by 5.0 °C/W junction-to-end-cap thermal resistance. It meets IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and select IEC61000-4-5 lightning secondary effects standards - verified under MIL-STD-750 Method 1020 for ESD insensitivity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 8.4 V - maximum continuous reverse/forward voltage before conduction begins; sets operating margin below breakdown. |
| V(BR) @ I(BR) | 10.45 V at 125 mA - precise threshold where avalanche conduction initiates; enables predictable turn-on timing. |
| VC @ IPP | 15.6 V at 96.2 A - clamped voltage during 10/1000 µs surge; defines worst-case overvoltage seen by protected ICs. |
| PPP | 1500 W - peak impulse power dissipation capability; determines survivability against high-energy transients. |
| IPP | 96.2 A - maximum non-repetitive surge current; directly constrains PCB trace sizing and fuse coordination. |
| αV(BR) | 0.07 %/°C - low temperature drift ensures consistent clamping across -55°C to +175°C operational range. |
| TJ/TSTG | -55°C to +175°C - extended military-grade temperature envelope supports operation in engine bays and space-constrained radomes. |
Pinout & Package
SQ-MELF (C-package) surface-mount hermetically sealed glass case with tin/lead-plated copper terminals; no polarity marking due to bidirectional symmetry; weight ≈1100 mg; dimensions per Microsemi T4-LDS-0278-1 Rev. 2: BD = 0.183–0.202", BL = 0.205–0.245", ECT = 0.019–0.028".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode/Cathode (symmetrical) | Bidirectional avalanche junction | Either end functions identically as conduction path during positive or negative transients; no orientation required on PCB. |
| End Cap (both ends) | Thermal and electrical termination | Directly interfaces with PCB pads for heat dissipation and low-inductance surge current return path. |
Key Features
| Feature | Design Value |
|---|---|
| Voidless hermetic glass seal | Eliminates internal moisture and particle migration - prevents parametric shift and latent failure in vacuum or high-humidity environments. |
| Category 1 metallurgical bonds | Ensures mechanical integrity under thermal cycling and shock/vibe; validated for MIL-PRF-19500/516 JAN-level reliability screening. |
| Triple-layer passivation | Protects junction surface from contamination and ion migration - maintains stable V(BR) and leakage performance over lifetime. |
| MIL-PRF-19500/516 qualification | Confirms compliance with military surge, life test, and environmental stress requirements - eliminates need for additional qualification testing. |
Applications
| Avionics Power Bus Protection | Radar Front-End ESD Hardening |
|---|---|
Use Scenario: Protecting 28 V DC aircraft power distribution networks from load dump and inductive switching spikes. IC Role / Device Role / Timing Role: Bidirectional clamping element placed at power entry point to limit transient overvoltage to <15.6 V. Use Value: Prevents latch-up or gate oxide rupture in downstream DC-DC controllers and FPGAs during MIL-STD-704A transients. | Use Scenario: Shielding RF receiver LNA inputs from ESD events during antenna handling or lightning-induced coupling. IC Role / Device Role / Timing Role: Fast-response (<1 ns) voltage clamp shunting ESD current away from sensitive GaAs MMICs. Use Value: Maintains signal integrity and avoids permanent damage to sub-100 nm input transistors under IEC61000-4-2 ±15 kV contact discharge. |
| Tactical Radio Transceiver Protection | Spacecraft Payload Interface Protection |
Use Scenario: Safeguarding HF/VHF transceiver PA output stages from antenna mismatch surges and EMP coupling. IC Role / Device Role / Timing Role: High-energy (1500 W) transient absorber mounted directly at RF connector feedthrough. Use Value: Enables uninterrupted transmission during field-deployed operation without derating for altitude or temperature extremes. | Use Scenario: Isolating scientific instrument data lines from spacecraft bus transients induced by solar array switching. IC Role / Device Role / Timing Role: Radiation-hardened (per MicroNote 050) TVS suppressing coupled noise on LVDS and RS-422 links. Use Value: Guarantees data integrity across mission duration without parametric drift or single-event burnout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 1N6143AUS | Commercial-grade version; same VWM, V(BR), VC, and PPP but lacks MIL-PRF-19500/516 qualification and Category 1 bonding. | Not suitable for flight-critical systems; acceptable for ground-test equipment or non-safety-critical subsystems. | Select when full military screening is unnecessary and cost sensitivity outweighs long-term reliability requirements. |
| JANTXV1N6143US | Same SQ-MELF package and electrical specs, but qualified to JANTXV level - includes extended burn-in, hermeticity testing, and lot traceability beyond JAN. | Required for Class S space programs and DoD Tier-1 avionics where zero-defect history is mandated. | Choose when program specifications require JANTXV-level documentation, radiation hardness validation, or 100% lot acceptance testing. |
Compared with 1N6143AUS and JANTXV1N6143US, JAN1N6143US/TR provides the optimal balance of military reliability assurance and production scalability - delivering verified Category 1 bond integrity and hermetic seal performance without the extended test overhead of JANTXV, making it ideal for volume-deployed tactical platforms.
Availability
JAN1N6143US/TR is available at Aetrix Electronics and suitable for avionics power bus protection, radar front-end ESD hardening, and tactical radio transceiver protection requiring stable component supply across extended production lifecycles and defense procurement cycles.
Supply support for JAN1N6143US/TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) designs high-reliability analog and mixed-signal semiconductors for aerospace, defense, and industrial markets, with emphasis on radiation-hardened, high-temperature, and MIL-spec components.
The JAN1N6143US/TR belongs to Microsemi's legacy military TVS family engineered specifically for survivability in harsh electromagnetic environments - targeting applications where single-point failure is unacceptable and parametric stability over temperature and time is mandatory.
FAQ
What is the clamping voltage of JAN1N6143US/TR and how does it protect downstream circuitry?
The JAN1N6143US/TR has a maximum clamping voltage (VC) of 15.6 V at 96.2 A peak pulse current (10/1000 µs). This value defines the upper voltage limit imposed on protected circuits during surge events. By limiting overvoltage to ≤15.6 V, the JAN1N6143US/TR prevents gate oxide breakdown in MOSFET drivers, latch-up in microcontrollers, and damage to precision analog front-ends - ensuring system-level robustness without requiring additional series impedance or filtering.
Is JAN1N6143US/TR RoHS compliant?
No, JAN1N6143US/TR is not RoHS compliant. Per Microsemi T4-LDS-0278-1 Rev. 2, RoHS-compliant matte-tin terminations are available only on commercial-grade versions (e.g., 1N6143AUS). The JAN1N6143US/TR uses standard tin/lead plating to meet MIL-PRF-19500/516 solderability and thermal cycling requirements, and its qualification excludes RoHS compliance.
What is the meaning of "JAN" prefix in JAN1N6143US/TR?
The "JAN" prefix in JAN1N6143US/TR denotes Joint Army-Navy qualification per MIL-PRF-19500/516 at the lowest military reliability level - including screening for hermeticity, temperature cycling, and surge endurance. It confirms that the JAN1N6143US/TR has passed baseline military tests and is approved for use in defense systems where commercial parts are prohibited, though it does not include the extended burn-in or lot traceability of JANTX or JANTXV variants.
How does the SQ-MELF package of JAN1N6143US/TR improve thermal performance compared to axial-leaded equivalents?
The SQ-MELF package of JAN1N6143US/TR provides a 5.0 °C/W junction-to-end-cap thermal resistance - significantly lower than axial-leaded versions due to direct end-cap solder attachment and absence of leadframe thermal bottlenecks. This enables higher sustained power dissipation during repetitive surges and improves reliability in compact, thermally constrained layouts typical of modern avionics modules where JAN1N6143US/TR is commonly deployed.
Can JAN1N6143US/TR be used in place of JAN1N6142US/TR or JAN1N6144US/TR?
No - JAN1N6143US/TR is not interchangeable with JAN1N6142US/TR (VWM = 7.6 V) or JAN1N6144US/TR (VWM = 9.1 V) without circuit revalidation. Each variant targets a specific working standoff voltage window; substituting alters the conduction margin relative to system operating voltage and may cause premature clamping or insufficient protection. The JAN1N6143US/TR must be selected based on exact 8.4 V VWM requirement.
JAN1N6143US/TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- SQ-MELF, C
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 8.4V
- Voltage - Breakdown (Min):
- 10.45V
- Voltage - Clamping (Max) @ Ipp:
- 15.6V
- Current - Peak Pulse (10/1000µs):
- 96.2A
- Power - Peak Pulse:
- 1500W (1.5kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500/516
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- C, SQ-MELF
JAN1N6143US/TR FAQ
1.How can I place an order for JAN1N6143US/TR through Aetrix?
Please submit a Request for Quotation (RFQ) for JAN1N6143US/TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JAN1N6143US/TR reliable?
The price and inventory of JAN1N6143US/TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JAN1N6143US/TR is usually 5 days.
3.What payment methods are accepted for JAN1N6143US/TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JAN1N6143US/TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JAN1N6143US/TR?
JAN1N6143US/TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JAN1N6143US/TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JAN1N6143US/TR?
For technical support, including JAN1N6143US/TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JAN1N6143US/TR requirements.
6.How does Aetrix verify that JAN1N6143US/TR is sourced from the original manufacturer or authorized distributors?
All JAN1N6143US/TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JAN1N6143US/TR meets industry standards.
7.What is the process for return or replacement of JAN1N6143US/TR?
All JAN1N6143US/TR units undergo pre-shipment inspection (PSI). If there is an issue with JAN1N6143US/TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JAN1N6143US/TR part is unused and in its original packaging.
Return procedure for JAN1N6143US/TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JAN1N6143US/TR Tags

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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