Microchip Technology JAN1N6145AUS/TR
- Part No.:
- JAN1N6145AUS/TR
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- SQ-MELF, C
- Datasheet:
-
JAN1N6145AUS/TR.pdf
- Description:
- BI-DIRECTIONAL TVS
- Quantity:
- Payment:

- Shipping:

Inventory:6,067
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Product details
Overview
JAN1N6145AUS/TR from Microsemi is a military-qualified, voidless hermetically sealed bidirectional Transient Voltage Suppressor (TVS) in SQ-MELF package, rated for 1500 W peak pulse power (10/1000 µs), 9.9 V working standoff voltage (VWM), and 18.2 V clamping voltage (VC) at 82.4 A peak pulse current - deployed in avionics power bus protection and radar front-end ESD hardening.
For engineers reviewing the JAN1N6145AUS/TR datasheet, JAN1N6145AUS/TR pinout, JAN1N6145AUS/TR application, or JAN1N6145AUS/TR equivalent, key selection criteria include MIL-PRF-19500/516 qualification level (JAN), bidirectional clamping symmetry, glass-body thermal resistance (5.0 °C/W), and IEC61000-4-2/4-4/4-5 compliance for high-reliability transient suppression.
Technical Context
This device operates as a bidirectional avalanche diode with no polarity marking, leveraging Category 1 metallurgical bonds and triple-layer passivation to sustain repeated 1500 W transients without degradation. Its 9.9 V VWM and 12.35 V minimum breakdown voltage (VBR @ 100 mA) define precise overvoltage thresholding in DC power rails.
Thermal design relies on junction-to-end-cap resistance of 5.0 °C/W, enabling stable operation up to +175 °C junction temperature. It meets MIL-STD-750 Method 1020 for ESD insensitivity and exhibits inherent radiation hardness per MicroNote 050.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 9.9 V - Maximum continuous DC voltage applied without conduction; sets operating margin before clamping onset. |
| VC @ IPP | 18.2 V at 82.4 A - Clamped voltage during 10/1000 µs surge; defines worst-case rail excursion under fault. |
| Peak Pulse Power | 1500 W - Sustains lightning-induced surges per IEC61000-4-5 Level 3 without failure. |
| VBR min | 12.35 V @ 100 mA - Guaranteed avalanche initiation voltage; ensures consistent turn-on across temperature. |
| TJ/TSTG | –55 °C to +175 °C - Enables deployment in missile guidance systems and satellite power conditioning. |
| αV(BR) | 0.08 %/°C - Predictable VBR drift over temperature; supports stable protection thresholds in wide-temp environments. |
Pinout & Package
SQ-MELF (Square-End-Cap Metal Electrode Leadless Face) glass package with two symmetrical end-cap terminals; hermetically sealed, voidless construction; weight ≈ 1100 mg; RoHS-compliant matte-tin plating available only on commercial-grade variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode/End Cap A | Bidirectional avalanche terminal | Identical electrical role to Cathode; no polarity marking required; symmetric clamping in either direction. |
| Cathode/End Cap B | Bidirectional avalanche terminal | Functionally identical to Anode; enables placement without orientation check; simplifies automated assembly. |
Key Features
| Feature | Design Value |
|---|---|
| JAN reliability level | Qualified to MIL-PRF-19500/516 for mission-critical aerospace and defense systems requiring zero-failure tolerance. |
| Voidless hermetic seal | Eliminates internal moisture ingress and bond degradation over 20+ year service life in humid or vacuum environments. |
| Category 1 metallurgical bonds | Ensures mechanical integrity under shock/vibration (MIL-STD-883 Method 2002) and thermal cycling (–55 °C to +125 °C). |
| Triple-layer passivation | Prevents surface leakage and premature breakdown under high-humidity or salt-spray conditions (MIL-STD-810G). |
Applications
| Avionics Power Bus Protection | Radar Front-End ESD Hardening |
|---|---|
Use Scenario: Suppresses load dump and coupling transients on 28 V DC aircraft power distribution networks. IC Role / Device Role / Timing Role: Bidirectional TVS clamping element placed across bus inputs to limit voltage excursions to <18.2 V. Use Value: Prevents latch-up in FPGAs and ADCs by holding rail voltage within ±10% of nominal during 1500 W surges. | Use Scenario: Shields LNA and mixer inputs in airborne pulse-Doppler radar receivers from ESD events. IC Role / Device Role / Timing Role: Fast-response transient suppressor mounted directly at RF connector feedthrough points. Use Value: Maintains signal integrity by limiting ESD-induced voltage overshoot to <18.2 V within <1 ns response time. |
| Military Vehicle Data Link Interfaces | Satellite Power Conditioning Units |
Use Scenario: Protects RS-422/485 transceivers in armored vehicle C4I systems against induced lightning surges. IC Role / Device Role / Timing Role: Bidirectional clamp on differential data lines referenced to chassis ground. Use Value: Ensures communication continuity by surviving >1000 IEC61000-4-5 Level 4 surges without parameter shift. | Use Scenario: Guards DC-DC converter inputs in LEO satellite EPS against secondary lightning effects and SEU-induced transients. IC Role / Device Role / Timing Role: Primary overvoltage clamp on 28 V bus feeding radiation-hardened PMICs. Use Value: Delivers proven radiation hardness (per MicroNote 050) and 175 °C operational capability in uncooled orbital environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient voltage suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 1N6145AUS | Commercial-grade version; same VWM, VC, and PPP but lacks JAN-level screening and MIL-PRF-19500/516 qualification. | Approved for non-mission-critical industrial controls; not cleared for flight hardware or nuclear command systems. | Select when cost sensitivity outweighs mandatory military qualification and full radiation hardness is not required. |
| JANTX1N6145AUS | Higher screening level than JAN: includes extended burn-in, parametric lot acceptance testing, and tighter VBR limits (±5% vs JAN's ±10%). | Required for Class S spaceflight components and DoD Tier 1 avionics where failure probability must be <1×10−6. | Choose when system safety integrity level (ASIL D or DAL A) mandates enhanced process control and traceability. |
Compared with JAN1N6145AUS/TR, the commercial 1N6145AUS reduces procurement cost and lead time but forfeits MIL-qualified reliability evidence, while JANTX1N6145AUS adds screening rigor and tighter parametric bounds at higher unit cost and longer qualification cycles.
Availability
JAN1N6145AUS/TR is available at Aetrix Electronics and suitable for avionics power bus protection, radar front-end ESD hardening, and military vehicle data link interfaces requiring stable component supply across extended production lifecycles.
Supply support for JAN1N6145AUS/TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) designs high-reliability analog and mixed-signal semiconductors for aerospace, defense, and industrial markets, with emphasis on radiation-hardened and MIL-spec components.
The JAN1N6145AUS/TR belongs to Microsemi's legacy 1N61xxAUS TVS family, engineered specifically for military-grade transient suppression in harsh-environment platforms where failure is not an option.
FAQ
What is the clamping voltage of JAN1N6145AUS/TR and how is it measured?
The clamping voltage (VC) of JAN1N6145AUS/TR is 18.2 V, measured at 82.4 A peak pulse current (IPP) using a standardized 10/1000 µs double-exponential waveform per IEC61000-4-5. This value reflects the maximum voltage seen across the device during surge conduction and is guaranteed across the full –55 °C to +175 °C junction temperature range. JAN1N6145AUS/TR maintains this clamping performance due to its Category 1 metallurgical bonds and voidless glass construction.
Is JAN1N6145AUS/TR RoHS compliant?
No, JAN1N6145AUS/TR is not RoHS compliant. Per the datasheet, RoHS-compliant matte-tin plating is available only on commercial-grade versions (e.g., 1N6145AUS), not on JAN-level qualified parts. The JAN1N6145AUS/TR uses traditional tin/lead plating over copper terminals to meet MIL-PRF-19500/516 solderability and reliability requirements, including compatibility with legacy military assembly processes.
What does the "A" suffix in JAN1N6145AUS/TR signify?
Per Microsemi's nomenclature, the "A" suffix in JAN1N6145AUS/TR indicates standard voltage tolerance: ±10% on VBR, ±5% on VC, and ±10% on IPP. Non-A versions (e.g., JAN1N6145US) have 5% higher VC, 5% lower minimum VBR, and 5% lower IPP. The "TR" denotes tape-and-reel packaging per EIA-481-B, and "JAN" specifies the lowest military reliability level per MIL-PRF-19500/516.
How does JAN1N6145AUS/TR differ from commercial 1N6145AUS in thermal performance?
JAN1N6145AUS/TR and commercial 1N6145AUS share identical thermal resistance (RθJEC = 5.0 °C/W) and junction temperature range (–55 °C to +175 °C), but JAN1N6145AUS/TR undergoes additional thermal cycling validation (MIL-STD-883 Method 1010) and burn-in to ensure stability under sustained thermal stress. The JAN1N6145AUS/TR's hermetic seal and Category 1 bonds prevent parameter drift after 1000 cycles between –55 °C and +125 °C.
Can JAN1N6145AUS/TR be used in bidirectional AC line protection?
Yes, JAN1N6145AUS/TR is inherently bidirectional and suitable for AC line protection where peak working voltage remains ≤9.9 V RMS (e.g., low-voltage sensor signal lines or auxiliary control circuits). Its symmetrical VBR and clamping behavior enable equal protection in both polarities. However, it is not rated for mains-voltage AC applications (e.g., 120/240 VAC) due to insufficient VWM; for such use, higher-VWM variants like JAN1N6169AUS (98.8 V) are specified.
JAN1N6145AUS/TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- SQ-MELF, C
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 9.9V
- Voltage - Breakdown (Min):
- 12.35V
- Voltage - Clamping (Max) @ Ipp:
- 18.2V
- Current - Peak Pulse (10/1000µs):
- 82.4A
- Power - Peak Pulse:
- 1500W (1.5kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500/516
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- C, SQ-MELF
JAN1N6145AUS/TR FAQ
1.How can I place an order for JAN1N6145AUS/TR through Aetrix?
Please submit a Request for Quotation (RFQ) for JAN1N6145AUS/TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JAN1N6145AUS/TR reliable?
The price and inventory of JAN1N6145AUS/TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JAN1N6145AUS/TR is usually 5 days.
3.What payment methods are accepted for JAN1N6145AUS/TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JAN1N6145AUS/TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JAN1N6145AUS/TR?
JAN1N6145AUS/TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JAN1N6145AUS/TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JAN1N6145AUS/TR?
For technical support, including JAN1N6145AUS/TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JAN1N6145AUS/TR requirements.
6.How does Aetrix verify that JAN1N6145AUS/TR is sourced from the original manufacturer or authorized distributors?
All JAN1N6145AUS/TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JAN1N6145AUS/TR meets industry standards.
7.What is the process for return or replacement of JAN1N6145AUS/TR?
All JAN1N6145AUS/TR units undergo pre-shipment inspection (PSI). If there is an issue with JAN1N6145AUS/TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JAN1N6145AUS/TR part is unused and in its original packaging.
Return procedure for JAN1N6145AUS/TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JAN1N6145AUS/TR Tags

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