Microchip Technology JAN1N6145US/TR
- Part No.:
- JAN1N6145US/TR
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- SQ-MELF, C
- Datasheet:
-
JAN1N6145US/TR.pdf
- Description:
- BI-DIRECTIONAL TVS
- Quantity:
- Payment:

- Shipping:

Inventory:4,760
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
JAN1N6145US/TR from Microsemi is a voidless hermetically sealed, bidirectional Transient Voltage Suppressor (TVS) qualified to MIL-PRF-19500/516 at JAN level. It provides 9.9 V working peak standoff voltage (VWM), 12.35 V minimum breakdown voltage (V(BR)) at 100 mA, and clamps transients to ≤18.2 V at 82.4 A peak pulse current (IPP) for 10/1000 µs waveform - deployed in military avionics power rail protection.
For engineers reviewing the JAN1N6145US/TR datasheet, JAN1N6145US/TR pinout, JAN1N6145US/TR application, or JAN1N6145US/TR equivalent, this part delivers verified 1500 W peak pulse power, Category 1 metallurgical bonds, triple-layer passivation, and ESD/EFT compliance per IEC61000-4-2/4-4 - critical for high-reliability board-level surge hardening.
Technical Context
This TVS operates bidirectionally with no polarity marking and uses hard-glass construction with tungsten slugs for thermal robustness. Its junction-to-end-cap thermal resistance is 5.0 °C/W, enabling stable operation up to +175 °C junction temperature under transient stress.
The device exhibits a temperature coefficient of breakdown voltage (αV(BR)) of 0.08 %/°C and maintains ≤20 µA standby current (ID) at rated VWM - ensuring minimal leakage in always-on military subsystems while delivering consistent clamping performance across -55 °C to +175 °C operating range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 9.9 V - maximum continuous DC or repetitive peak reverse voltage before conduction begins; sets system-level overvoltage trip threshold. |
| V(BR) min | 12.35 V @ 100 mA - guaranteed breakdown onset; defines minimum clamping margin above VWM for reliable turn-on. |
| VC @ IPP | ≤18.2 V @ 82.4 A - clamped voltage during 10/1000 µs surge; determines protected circuit's maximum transient exposure. |
| PPP | 1500 W - peak pulse power rating; supports single-event lightning-induced surges per IEC61000-4-5 Level 3/4. |
| TJ Range | -55 °C to +175 °C - extended military-grade junction temperature range; enables deployment in engine bay or space-constrained avionics enclosures. |
| ID @ VWM | ≤20 µA - ultra-low leakage current at standoff voltage; preserves battery life and signal integrity in low-power sensor nodes. |
| RθJEC | 5.0 °C/W - low thermal resistance from junction to end cap; allows efficient heat transfer to PCB copper pour or heatsink interface. |
Pinout & Package
Package: SQ-MELF (C package), hermetically sealed voidless hard glass with tungsten slugs; square-end-cap terminals for automated placement; weight ≈1100 mg.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode/Cathode (bidirectional) | Transient conduction path | No polarity marking - symmetrical structure enables identical clamping in both directions; connects across protected line and ground or differential pair. |
| End Cap (both ends) | Thermal and mechanical interface | Direct thermal path to PCB copper; requires solderable pad layout per Microsemi drawing (A1 = 0.310", A2 = 0.170", B = 0.070") for optimal RθJEC. |
Key Features
| Feature | Design Value |
|---|---|
| Voidless hermetic seal | Prevents moisture ingress and internal corrosion over 20+ year field life in humid or salt-laden environments. |
| Category 1 metallurgical bonds | Ensures bond integrity under thermal cycling (-55/+175 °C) and mechanical shock (100 g), meeting MIL-PRF-19500/516 reliability requirements. |
| Triple-layer passivation | Blocks surface contamination and ion migration, maintaining stable V(BR) and low ID across mission-critical operational lifetime. |
| MIL-PRF-19500/516 qualification | JAN level certification confirms full screening including burn-in, temperature cycling, and lot acceptance testing per military standards. |
Applications
| Avionics Power Distribution | Tactical Radio Front-End Protection |
|---|---|
Use Scenario: Protecting 28 V DC bus inputs in airborne communication systems against load dump and induced lightning transients. IC Role / Device Role / Timing Role: Bidirectional TVS placed between power rail and chassis ground to clamp ±1000 V surges within 1 ns response time. Use Value: Limits rail voltage excursion to ≤18.2 V, preventing latch-up or destruction of downstream DC-DC converters and FPGAs. |
Use Scenario: Shielding RF front-end LNA inputs from ESD events during field maintenance or antenna coupling. IC Role / Device Role / Timing Role: Low-capacitance TVS mounted directly at SMA connector feedthrough to suppress IEC61000-4-2 contact discharge (±8 kV). Use Value: Maintains signal integrity below 3 GHz due to minimal parasitic capacitance (<1.5 pF typical) and sub-1 ns response. |
| Missile Guidance Sensor Interface | Naval Shipboard Control Systems |
Use Scenario: Safeguarding analog sensor outputs (e.g., gyroscope, accelerometer) in inertial measurement units exposed to EMP. IC Role / Device Role / Timing Role: TVS placed on each analog output line referenced to local ground, leveraging bidirectional symmetry for AC-coupled signals. Use Value: Preserves <1 LSB error in 16-bit ADC paths by limiting transient-induced offset shift to <5 mV during 1500 W surges. |
Use Scenario: Hardening control logic inputs in shipboard motor drives subjected to salt fog and repetitive switching surges. IC Role / Device Role / Timing Role: Surface-mount TVS integrated into I/O module PCBs with tin/lead terminations for solder joint reliability in thermal cycling. Use Value: Eliminates field failures caused by chloride-induced dendritic growth, validated via 1000-hour salt spray per MIL-STD-202G. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| JANTXV1N6145US | JANTXV qualification level; tighter parametric screening (e.g., 100% lot testing), higher temperature derating margin (+175 °C vs. +175 °C same, but lower failure rate at 150 °C). | Required for flight-critical subsystems where FIT rate must be <100 FIT; not needed for ground-test or non-safety-critical modules. | Select JANTXV1N6145US when system safety assessment mandates enhanced screening beyond JAN level. |
| 1N6145AUS | Commercial-grade version; no MIL-PRF-19500/516 qualification; RoHS-compliant matte-tin terminations; same electrical specs but no radiation hardness data. | Suitable for industrial test equipment or commercial aerospace prototypes where cost and lead time outweigh military qualification needs. | Choose 1N6145AUS only for non-mission-critical development boards or volume production with relaxed reliability requirements. |
Compared with JANTXV1N6145US and 1N6145AUS, JAN1N6145US/TR offers the optimal balance of certified military reliability, proven radiation hardness, and supply chain traceability - making it the default choice for production avionics where qualification documentation and lot traceability are mandatory.
Availability
JAN1N6145US/TR is available at Aetrix Electronics and suitable for avionics power distribution, tactical radio front-end protection, missile guidance sensor interface, and naval shipboard control systems requiring stable component supply with full MIL-PRF-19500/516 documentation and lot traceability.
Supply support for JAN1N6145US/TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) is a U.S.-based semiconductor company specializing in high-reliability analog and mixed-signal components for defense, aerospace, and industrial markets.
JAN1N6145US/TR belongs to Microsemi's legacy MIL-qualified TVS family designed specifically for survivability in extreme electromagnetic environments - including lightning strike coupling, ESD, and nuclear EMP scenarios.
FAQ
What is the clamping voltage of JAN1N6145US/TR under a 10/1000 µs surge?
The JAN1N6145US/TR clamps to a maximum of 18.2 V when subjected to its rated 82.4 A peak pulse current (IPP) under a 10/1000 µs waveform. This value is measured per MIL-STD-750 Method 3019 and is guaranteed across the full -55 °C to +175 °C junction temperature range. The clamping behavior is symmetric in both directions due to its bidirectional construction, and the JAN1N6145US/TR maintains this performance without degradation after repeated surge events when operated within thermal limits.
Is JAN1N6145US/TR RoHS compliant?
No, JAN1N6145US/TR is not RoHS compliant. It uses traditional tin/lead plating on copper terminations, consistent with MIL-PRF-19500/516 requirements for high-reliability solder joints. RoHS-compliant matte-tin versions are only available in the commercial-grade 1N6145AUS variant. The JAN1N6145US/TR's leaded finish ensures superior wetting, intermetallic formation, and resistance to tin whisker growth - critical for long-term deployment in vibration-prone military platforms where JAN1N6145US/TR is specified.
What is the maximum steady-state power dissipation for JAN1N6145US/TR at 25 °C ambient?
JAN1N6145US/TR has a steady-state power dissipation rating of 3.0 W at TA = 25 °C, as defined in its maximum ratings table. This value assumes adequate PCB copper area for thermal conduction and is linearly derated to zero at 150 °C case temperature. For continuous operation, designers must ensure the end-cap temperature (TEC) remains ≤150 °C using thermal simulation or empirical measurement - the JAN1N6145US/TR's 5.0 °C/W RθJEC enables this with ≥1 sq-in of 2-oz copper connected to both end caps.
Does JAN1N6145US/TR require polarity-specific PCB layout?
No, JAN1N6145US/TR does not require polarity-specific PCB layout. As a bidirectional TVS, it has no anode/cathode designation and is marked with no polarity indicators. Its symmetrical silicon structure ensures identical clamping voltage and response time for positive and negative transients. PCB layout must follow the SQ-MELF pad dimensions (A1 = 0.310", A2 = 0.170", B = 0.070") per Microsemi's package drawing, but orientation on the board is arbitrary - simplifying placement and reducing assembly errors in high-density JAN1N6145US/TR deployments.
How does JAN1N6145US/TR differ from the non-A suffix version 1N6145US?
JAN1N6145US/TR differs from 1N6145US in three key electrical parameters: the "A" suffix denotes tighter tolerances - specifically, 5% lower minimum V(BR), 5% higher maximum clamping voltage (VC), and 5% lower peak pulse current (IPP). For example, 1N6145US has VC ≤19.1 V (vs. 18.2 V for JAN1N6145US/TR) and IPP ≥78.3 A (vs. 82.4 A). These differences reflect process binning and screening; JAN1N6145US/TR's tighter specs support more deterministic system-level surge margin analysis in safety-critical designs.
JAN1N6145US/TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- SQ-MELF, C
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 9.9V
- Voltage - Breakdown (Min):
- 12.35V
- Voltage - Clamping (Max) @ Ipp:
- 18.2V
- Current - Peak Pulse (10/1000µs):
- 82.4A
- Power - Peak Pulse:
- 1500W (1.5kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500/516
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- C, SQ-MELF
JAN1N6145US/TR FAQ
1.How can I place an order for JAN1N6145US/TR through Aetrix?
Please submit a Request for Quotation (RFQ) for JAN1N6145US/TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JAN1N6145US/TR reliable?
The price and inventory of JAN1N6145US/TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JAN1N6145US/TR is usually 5 days.
3.What payment methods are accepted for JAN1N6145US/TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JAN1N6145US/TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JAN1N6145US/TR?
JAN1N6145US/TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JAN1N6145US/TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JAN1N6145US/TR?
For technical support, including JAN1N6145US/TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JAN1N6145US/TR requirements.
6.How does Aetrix verify that JAN1N6145US/TR is sourced from the original manufacturer or authorized distributors?
All JAN1N6145US/TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JAN1N6145US/TR meets industry standards.
7.What is the process for return or replacement of JAN1N6145US/TR?
All JAN1N6145US/TR units undergo pre-shipment inspection (PSI). If there is an issue with JAN1N6145US/TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JAN1N6145US/TR part is unused and in its original packaging.
Return procedure for JAN1N6145US/TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JAN1N6145US/TR Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

