Microchip Technology JAN1N6156US/TR
- Part No.:
- JAN1N6156US/TR
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- SQ-MELF, C
- Datasheet:
-
JAN1N6156US/TR.pdf
- Description:
- BI-DIRECTIONAL TVS
- Quantity:
- Payment:

- Shipping:

Inventory:5,451
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
JAN1N6156US/TR from Microsemi is a military-qualified, voidless hermetically sealed bidirectional Transient Voltage Suppressor (TVS) in SQ-MELF package, rated for 1500 W peak pulse power (10/1000 µs), 29.7 V working standoff voltage (VWM), and 53.6 V clamping voltage (VC) at 28.0 A peak pulse current - deployed in avionics power bus protection and radar front-end surge suppression.
For engineers reviewing the JAN1N6156US/TR datasheet, JAN1N6156US/TR pinout, JAN1N6156US/TR application, or JAN1N6156US/TR equivalent, this page delivers verified military-grade TVS specifications, MIL-PRF-19500/516 qualification status, thermal derating curves, clamping behavior under lightning-induced transients, and RoHS-compliant commercial variants.
Technical Context
This device operates as a bidirectional avalanche diode with no polarity marking, leveraging hard-glass hermetic sealing and Category 1 metallurgical bonds to sustain operation from −55 °C to +175 °C junction temperature. Its 5.0 °C/W junction-to-end-cap thermal resistance enables high-reliability mounting on thermally managed metal-core PCBs.
It meets IEC 61000-4-2 (ESD), IEC 61000-4-4 (EFT), and select levels of IEC 61000-4-5 (lightning surge) - validated via 10/1000 µs waveform testing. Standby current remains ≤5 µA at 29.7 VWM, and breakdown occurs at minimum 37.1 VBR @ 30 mA per MIL-STD-202 test method 305.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 29.7 V - maximum continuous reverse voltage before leakage exceeds 5 µA; sets operating margin below clamping threshold |
| VC @ IPP | 53.6 V @ 28.0 A - clamped voltage during 10/1000 µs surge; defines worst-case overvoltage seen by protected IC |
| PPP | 1500 W - peak pulse power handling for standardized lightning surge waveform; determines survivability of MIL-STD-461 CS115 events |
| TJ Range | −55 °C to +175 °C - qualified junction temperature range per MIL-PRF-19500/516; supports extended-range aerospace deployments |
| RθJEC | 5.0 °C/W - thermal resistance from junction to end cap; enables direct heatsinking to chassis or cold plate without solder pad thermal relief |
| αVBR | 0.095 %/°C - temperature coefficient of breakdown voltage; ensures stable VBR drift < ±1.5% across full military temp range |
Pinout & Package
SQ-MELF (Square-End-Cap Metal Electrode Leadless Face) hermetically sealed glass package with tungsten slugs and tin/lead-plated copper terminals; no polarity marking; weight ≈1100 mg; dimensions: BD = 4.65–5.13 mm, BL = 5.21–6.22 mm, ECT = 0.48–0.71 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode/Cathode (Bidirectional) | Common transient conduction path | No polarity - symmetric avalanche structure conducts equally in both directions above VBR; eliminates orientation errors during automated placement |
| End Cap (Both Ends) | Thermal and electrical interface | Directly bonded to PCB copper pour or heatsink; serves as primary heat dissipation path and low-inductance return path for surge current |
Key Features
| Feature | Design Value |
|---|---|
| Voidless hermetic glass seal | Prevents moisture ingress and internal corrosion over 20+ year field life in humid, salt-laden environments (e.g., naval radar systems) |
| Category 1 metallurgical bonds | Guarantees bond integrity under mechanical shock ≥100 g and thermal cycling (−55 °C ↔ +125 °C, 1000 cycles) per MIL-STD-883 |
| Triple-layer passivation | Reduces surface leakage current to ≤5 µA at VWM, enabling reliable operation in high-impedance sensor bias networks |
| MIL-PRF-19500/516 qualification | Validates compliance with JAN-level screening including burn-in, temperature cycling, and lot acceptance testing for space-qualified hardware |
Applications
| Avionics Power Bus Protection | Radar Front-End Surge Suppression |
|---|---|
Use Scenario: Protecting 28 V DC aircraft power distribution lines against load dump and inductive switching transients. IC Role / Device Role / Timing Role: Bidirectional clamping element placed directly across bus rails to limit voltage excursions to ≤53.6 V during 1500 W surges. Use Value: Prevents latch-up or destruction of downstream DC-DC converters and FPGAs by holding rail voltage within 10% of nominal during MIL-STD-704A transient events. | Use Scenario: Shielding RF receiver LNA inputs from antenna-coupled lightning-induced surges in ground-based radar systems. IC Role / Device Role / Timing Role: Low-capacitance (<15 pF typical) transient clamp mounted at RF connector entry point, before impedance-matching network. Use Value: Maintains signal integrity up to 3 GHz while diverting >25 A surge current away from sensitive GaAs MMICs without degrading noise figure. |
| Spacecraft Command & Data Handling | Military Vehicle CAN Bus Interface |
Use Scenario: Safeguarding RS-422/RS-485 data links between flight computers and payload modules in LEO satellites. IC Role / Device Role / Timing Role: Bidirectional TVS installed on differential pair lines with matched layout to preserve common-mode rejection. Use Value: Survives total ionizing dose (TID) >100 krad(Si) and single-event burnout (SEB) up to 80 MeV·cm²/mg per MicroNote 050 radiation hardness data. | Use Scenario: Hardening 125 kbps CAN FD interfaces in armored vehicle control networks against EMP and ignition noise. IC Role / Device Role / Timing Role: Line-side transient suppressor placed adjacent to CAN transceiver, grounded to chassis via shortest possible path. Use Value: Clamps fast-rising transients (tr < 1 ns) to <55 V while maintaining CAN signal edge fidelity and meeting ISO 16750-2 pulse 5b immunity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| JANTXV1N6156US | Same electrical specs but JANTXV-level screening (enhanced burn-in, 100% parametric test, extended temperature cycling) | Required for Class S spaceflight hardware where JAN-level screening is insufficient | Select when mission-critical reliability demands zero latent defects and full traceability per MIL-PRF-19500/516 Appendix A |
| 1N6156AUS | Commercial-grade version; identical VWM, VC, PPP, but not MIL-qualified; RoHS-compliant matte-tin plating available | Suitable for non-military industrial controls where cost sensitivity outweighs radiation tolerance or long-term shelf life | Choose for volume production of ground-test equipment or commercial radar subsystems with relaxed qualification requirements |
Compared with JAN1N6156US/TR, JANTXV1N6156US adds screening rigor without altering clamping performance, while 1N6156AUS trades qualification for lower cost and RoHS compliance - enabling tiered sourcing across development, qualification, and production phases.
Availability
JAN1N6156US/TR is available at Aetrix Electronics and suitable for avionics power bus protection, radar front-end surge suppression, spacecraft command & data handling, and military vehicle CAN bus interface requiring stable component supply across extended lifecycle programs.
Supply support for JAN1N6156US/TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) designs high-reliability analog and mixed-signal semiconductors for aerospace, defense, and industrial markets, with emphasis on radiation-hardened, high-temperature, and MIL-spec components.
The JAN1N6156US/TR belongs to Microsemi's legacy 1N61xxAUS military TVS family, engineered specifically for survivability in extreme electromagnetic environments - including lightning strike coupling, nuclear EMP, and high-G mechanical shock scenarios.
FAQ
What is the clamping voltage of JAN1N6156US/TR at its rated peak pulse current?
The JAN1N6156US/TR has a maximum clamping voltage (VC) of 53.6 V at 28.0 A peak pulse current (IPP) under the standard 10/1000 µs double-exponential surge waveform. This value is measured per MIL-STD-202 Method 305 and defines the upper voltage bound imposed on protected circuitry during transient events. The JAN1N6156US/TR maintains this clamping performance across its full qualified temperature range of −55 °C to +175 °C.
Is JAN1N6156US/TR RoHS compliant?
No, JAN1N6156US/TR is not RoHS compliant. It uses traditional tin/lead plating on copper terminals per MIL-PRF-19500/516 requirements for solderability and reliability in high-reliability applications. RoHS-compliant matte-tin plating is only available on the commercial-grade variant 1N6156AUS, not on JAN-level parts. The JAN1N6156US/TR remains exempt under RoHS Annex III for military and aerospace applications requiring lead-based finishes.
What is the difference between JAN1N6156US/TR and 1N6156AUS?
JAN1N6156US/TR is fully MIL-PRF-19500/516 qualified to JAN level, including rigorous screening (burn-in, temperature cycling, lot acceptance tests), while 1N6156AUS is the commercial-grade counterpart with identical electrical specs but no military qualification. The JAN1N6156US/TR uses tin/lead plating; 1N6156AUS offers optional RoHS-compliant matte-tin. Both share the same SQ-MELF package and 29.7 VWM/53.6 VC ratings.
Does JAN1N6156US/TR have polarity markings?
No, JAN1N6156US/TR has no polarity markings because it is a bidirectional TVS diode. Its symmetrical avalanche structure conducts identically in both directions once the breakdown voltage (minimum 37.1 V) is exceeded. This eliminates orientation errors during automated placement and simplifies PCB layout - the device may be mounted in either direction across protected lines without affecting clamping behavior or reliability.
What is the thermal resistance specification for JAN1N6156US/TR?
JAN1N6156US/TR has a junction-to-end-cap thermal resistance (RθJEC) of 5.0 °C/W, measured per MIL-STD-750 Method 1022. This low thermal resistance enables efficient heat transfer from the silicon junction directly to the PCB copper pour or external heatsink via the end caps. It supports continuous off-state power dissipation up to 5.0 W at TEC = 150 °C, with linear derating to zero at 175 °C.
JAN1N6156US/TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- SQ-MELF, C
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 29.7V
- Voltage - Breakdown (Min):
- 37.1V
- Voltage - Clamping (Max) @ Ipp:
- 53.6V
- Current - Peak Pulse (10/1000µs):
- 28A
- Power - Peak Pulse:
- 1500W (1.5kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500/516
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- C, SQ-MELF
JAN1N6156US/TR FAQ
1.How can I place an order for JAN1N6156US/TR through Aetrix?
Please submit a Request for Quotation (RFQ) for JAN1N6156US/TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JAN1N6156US/TR reliable?
The price and inventory of JAN1N6156US/TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JAN1N6156US/TR is usually 5 days.
3.What payment methods are accepted for JAN1N6156US/TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JAN1N6156US/TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JAN1N6156US/TR?
JAN1N6156US/TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JAN1N6156US/TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JAN1N6156US/TR?
For technical support, including JAN1N6156US/TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JAN1N6156US/TR requirements.
6.How does Aetrix verify that JAN1N6156US/TR is sourced from the original manufacturer or authorized distributors?
All JAN1N6156US/TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JAN1N6156US/TR meets industry standards.
7.What is the process for return or replacement of JAN1N6156US/TR?
All JAN1N6156US/TR units undergo pre-shipment inspection (PSI). If there is an issue with JAN1N6156US/TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JAN1N6156US/TR part is unused and in its original packaging.
Return procedure for JAN1N6156US/TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JAN1N6156US/TR Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

