Microchip Technology JAN1N6168AUS/TR
- Part No.:
- JAN1N6168AUS/TR
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- SQ-MELF, C
- Datasheet:
-
JAN1N6168AUS/TR.pdf
- Description:
- BI-DIRECTIONAL TVS
- Quantity:
- Payment:

- Shipping:

Inventory:8,338
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
JAN1N6168AUS/TR from Microsemi is a voidless hermetically sealed, bidirectional Transient Voltage Suppressor (TVS) qualified to MIL-PRF-19500/516 at JAN level. It provides 91.2 V working standoff voltage (VWM), 114.0 V minimum breakdown voltage (V(BR)) at 10 mA, and clamps transients to 165.1 V at 9.1 A peak pulse current (IPP) for 10/1000 µs waveform - deployed in military avionics power rail protection.
For engineers reviewing the JAN1N6168AUS/TR datasheet, JAN1N6168AUS/TR pinout, JAN1N6168AUS/TR application, or JAN1N6168AUS/TR equivalent, key selection criteria include its 1500 W peak pulse power rating, -55°C to +175°C junction temperature range, Category 1 metallurgical bonds, RoHS-compliant tin/lead termination option, and SQ-MELF "C" package compatibility with surface-mount reflow.
Technical Context
This TVS operates bidirectionally with no polarity marking and relies on hard-glass construction with tungsten slugs for thermal stability. Its clamping behavior is defined by a 10/1000 µs double-exponential pulse, delivering 1500 W peak pulse power while maintaining <5 µA standby current at VWM.
The device uses internal Category 1 metallurgical bonds and triple-layer passivation to ensure reliability under radiation exposure and ESD stress per MIL-STD-750 Method 1020. Thermal resistance from junction to end cap is 5.0 °C/W, enabling robust operation up to 175 °C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 91.2 V - maximum continuous reverse/forward voltage before conduction begins; sets system operating margin. |
| V(BR) min | 114.0 V @ 10 mA - guaranteed breakdown onset; defines threshold for transient clamping activation. |
| VC @ IPP | 165.1 V @ 9.1 A - clamped voltage during 10/1000 µs surge; determines protected circuit's max overvoltage stress. |
| PPP | 1500 W - peak impulse power handling; supports lightning-induced surges per IEC61000-4-5 Level 3. |
| ID @ VWM | ≤5 µA - leakage current at rated standoff; ensures minimal power loss in always-on systems. |
| TJ Range | -55°C to +175°C - operational junction temperature span; validated for aerospace and missile guidance environments. |
| RθJEC | 5.0 °C/W - thermal resistance to end cap; enables direct heat sinking via PCB copper pour or metal mounting. |
Pinout & Package
Package: SQ-MELF "C" (hermetically sealed voidless hard glass with tungsten slugs); square-end-cap terminals for precise placement; weight ≈1100 mg; RoHS-compliant matte-tin available for commercial grade only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode/Cathode (bidirectional) | Transient conduction path | No polarity marking; symmetric conduction in either direction; both ends function identically as current entry/exit points during surge events. |
| End Cap (glass body contact) | Thermal interface | Primary heat dissipation path to PCB or heatsink; requires low-thermal-resistance mounting per Figure 6 derating curve. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping | Enables single-device protection of AC-coupled or floating signal/power lines without polarity concerns. |
| Category 1 metallurgical bonds | Guarantees bond integrity under thermal cycling and mechanical shock - required for MIL-PRF-19500/516 JAN qualification. |
| Triple-layer passivation | Prevents moisture ingress and surface leakage degradation in high-humidity or salt-fog environments. |
| Voidless hermetic seal | Eliminates internal delamination risk during reflow or long-term operation; critical for >20-year field life in space-grade systems. |
| IEC61000-4-2/4-4/4-5 compliance | Validated ESD (±15 kV air), EFT (±4 kV), and lightning surge (1.2/50 µs + 8/20 µs combo wave) immunity per test standards. |
Applications
| Avionics Power Distribution | Military Radar Signal Conditioning |
|---|---|
Use Scenario: Protection of 28 V DC bus inputs in airborne mission computers exposed to load dump and induced lightning transients. IC Role / Device Role / Timing Role: Bidirectional TVS placed across input rails to clamp surges before they reach DC/DC converters and FPGAs. Use Value: 1500 W PPP and 165.1 V clamping limit downstream IC damage during MIL-STD-704F transient events. |
Use Scenario: Front-end protection of RF receiver analog signal paths in ground-based radar systems operating in coastal environments. IC Role / Device Role / Timing Role: TVS shunting fast-rising ESD pulses on differential IF lines without distorting signal integrity. Use Value: <5 µA leakage at 91.2 V VWM prevents DC offset drift in precision gain stages; bidirectional symmetry avoids signal inversion. |
| Tactical Vehicle Communication Systems | Missile Guidance Control Units |
Use Scenario: CAN bus line protection in armored vehicle command modules subject to EMP and ignition noise. IC Role / Device Role / Timing Role: TVS mounted directly at connector entry point to suppress common-mode surges on shielded twisted-pair cables. Use Value: 114.0 V V(BR) ensures no false triggering during 24 V nominal bus fluctuations; -55°C to +175°C rating covers engine bay extremes. |
Use Scenario: Power rail protection in inertial measurement units (IMUs) inside guided munitions undergoing high-G launch acceleration. IC Role / Device Role / Timing Role: TVS safeguarding voltage regulators feeding gyroscopes and accelerometers against pyroshock-induced transients. Use Value: Voidless hermetic seal and Category 1 bonds prevent failure under 20,000 g shock profiles per MIL-STD-883 Method 2002. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient voltage suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| JAN1N6167AUS/TR | Lower VWM (86.6 V), lower VC (151.3 V @ 9.9 A), same 1500 W PPP and SQ-MELF package. | Suitable where system operating voltage is ≤25% below 91.2 V; tighter clamping margin but reduced standoff headroom. | Select when protecting 24 V or 48 V subsystems requiring lower clamping voltage without sacrificing surge rating. |
| JAN1N6169AUS/TR | Higher VWM (98.8 V), higher VC (178.8 V @ 8.4 A), same 1500 W PPP and SQ-MELF package. | Used where higher system voltage tolerance is needed, e.g., 115 VAC-derived DC rails or legacy 100 V telecom interfaces. | Choose for applications demanding greater standoff margin against sustained overvoltage, accepting higher clamping during surge. |
Compared with JAN1N6168AUS/TR, JAN1N6167AUS/TR offers lower clamping at reduced standoff, while JAN1N6169AUS/TR increases standoff headroom at the cost of higher clamping voltage - all three share identical thermal performance, qualification level, and package footprint.
Availability
JAN1N6168AUS/TR is available at Aetrix Electronics and suitable for avionics power distribution, military radar signal conditioning, tactical vehicle communication systems, and missile guidance control units requiring stable component supply across extended product lifecycles.
Supply support for JAN1N6168AUS/TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) designs high-reliability analog and mixed-signal semiconductors for aerospace, defense, and industrial markets, with emphasis on radiation-hardened and MIL-spec components.
JAN1N6168AUS/TR belongs to Microsemi's military-qualified TVS family engineered specifically for survivability in extreme electromagnetic environments - including lightning strike coupling, ESD events, and nuclear EMP scenarios.
FAQ
What is the maximum clamping voltage of JAN1N6168AUS/TR under a 10/1000 µs surge?
The maximum clamping voltage (VC) of JAN1N6168AUS/TR is 165.1 V when subjected to a 9.1 A peak pulse current (IPP) with a 10/1000 µs waveform. This value is measured per standard test conditions in the datasheet and defines the upper voltage limit imposed on protected circuits during transient events. JAN1N6168AUS/TR maintains this clamping performance across its full qualified temperature range.
Is JAN1N6168AUS/TR compatible with lead-free reflow soldering processes?
JAN1N6168AUS/TR supports standard surface-mount reflow profiles with a maximum solder temperature of 260 °C for 10 seconds, as specified in the datasheet. While the base termination is tin/lead, RoHS-compliant matte-tin versions are available for commercial-grade variants - however, the JAN-level JAN1N6168AUS/TR uses tin/lead plating and is qualified for use in controlled-temperature reflow processes meeting J-STD-020 requirements.
Does JAN1N6168AUS/TR require polarity-aware PCB layout?
No - JAN1N6168AUS/TR is a bidirectional TVS with no polarity marking and symmetric electrical characteristics in both directions. Its SQ-MELF "C" package has identical end-cap terminals, allowing orientation-agnostic placement on PCBs. This simplifies layout and eliminates risk of reverse installation in high-density military assemblies where manual inspection is limited.
How does JAN1N6168AUS/TR meet MIL-PRF-19500/516 qualification requirements?
JAN1N6168AUS/TR achieves MIL-PRF-19500/516 qualification at JAN level through voidless hermetic sealing, Category 1 metallurgical bonds, triple-layer passivation, and full environmental testing including thermal cycling, mechanical shock, and humidity exposure. The device undergoes lot-by-lot screening per MIL-STD-750 and is traceable to material lots and process controls documented in Microsemi's QML certification.
What is the steady-state power dissipation capability of JAN1N6168AUS/TR at 25 °C ambient?
At TA = 25 °C, JAN1N6168AUS/TR has a steady-state power dissipation rating (PD) of 3.0 W. This value assumes adequate thermal management - such as copper pour or thermal vias - to maintain junction temperature within limits. Derating is linear above 150 °C end-cap temperature, reaching zero at 175 °C, as shown in Figure 4 of the datasheet.
JAN1N6168AUS/TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- SQ-MELF, C
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 91.2V
- Voltage - Breakdown (Min):
- 114V
- Voltage - Clamping (Max) @ Ipp:
- 165.1V
- Current - Peak Pulse (10/1000µs):
- 9.1A
- Power - Peak Pulse:
- 1500W (1.5kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500/516
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- C, SQ-MELF
JAN1N6168AUS/TR FAQ
1.How can I place an order for JAN1N6168AUS/TR through Aetrix?
Please submit a Request for Quotation (RFQ) for JAN1N6168AUS/TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JAN1N6168AUS/TR reliable?
The price and inventory of JAN1N6168AUS/TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JAN1N6168AUS/TR is usually 5 days.
3.What payment methods are accepted for JAN1N6168AUS/TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JAN1N6168AUS/TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JAN1N6168AUS/TR?
JAN1N6168AUS/TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JAN1N6168AUS/TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JAN1N6168AUS/TR?
For technical support, including JAN1N6168AUS/TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JAN1N6168AUS/TR requirements.
6.How does Aetrix verify that JAN1N6168AUS/TR is sourced from the original manufacturer or authorized distributors?
All JAN1N6168AUS/TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JAN1N6168AUS/TR meets industry standards.
7.What is the process for return or replacement of JAN1N6168AUS/TR?
All JAN1N6168AUS/TR units undergo pre-shipment inspection (PSI). If there is an issue with JAN1N6168AUS/TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JAN1N6168AUS/TR part is unused and in its original packaging.
Return procedure for JAN1N6168AUS/TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JAN1N6168AUS/TR Tags

-
ESD9B5.0ST5G
onsemi

-
DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

