My Inquiry
My Account
Microchip Technology JAN1N6172AUS/TR
- Part No.:
- JAN1N6172AUS/TR
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- SQ-MELF, C
- Datasheet:
-
JAN1N6172AUS/TR.pdf
- Description:
- BI-DIRECTIONAL TVS
- Quantity:
- Payment:
- Shipping:
Inventory:2,588
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
JAN1N6172AUS/TR from Microsemi is a voidless hermetically sealed surface-mount bidirectional Transient Voltage Suppressor (TVS) qualified to MIL-PRF-19500/516 at JAN level, with 136.8 V working standoff voltage (VWM), 171.0 V minimum breakdown voltage (V(BR)), and 245.7 V clamping voltage (VC) at 6.1 A peak pulse current (IPP). It delivers 1500 W peak pulse power for 10/1000 µs transients and operates from –55 °C to +175 °C, used in military avionics power rail protection.
For engineers reviewing the JAN1N6172AUS/TR datasheet, JAN1N6172AUS/TR pinout, JAN1N6172AUS/TR application, or JAN1N6172AUS/TR equivalent, key selection criteria include clamping voltage margin relative to protected IC VDD, standoff voltage alignment with system DC bus, surge current handling under IEC61000-4-5 Level 4, and hermetic package suitability for high-reliability aerospace deployments.
Technical Context
This TVS employs hard-glass construction with internal Category 1 metallurgical bonds and triple-layer passivation to ensure radiation hardness and ESD immunity per MIL-STD-750 Method 1020. Its bidirectional architecture provides symmetrical clamping without polarity marking, enabling use on AC-coupled or floating signal lines.
Designed for transient suppression per IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and select IEC61000-4-5 lightning-induced surge levels, it maintains stable V(BR) with 0.110 %/°C temperature coefficient and supports steady-state off-state power up to 3.0 W at 25 °C ambient.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VWM | 136.8 V - Maximum continuous DC or repetitive peak voltage the device blocks without conduction. |
| V(BR) min | 171.0 V @ 5 mA - Minimum voltage at which the device enters avalanche breakdown, defining overvoltage trip threshold. |
| VC @ IPP | 245.7 V @ 6.1 A - Clamped voltage during 10/1000 µs surge, limiting stress on downstream circuitry. |
| PPP | 1500 W - Peak impulse power capability for standardized surge waveform, critical for lightning secondary effect mitigation. |
| TJ range | –55 °C to +175 °C - Full military-grade junction temperature operating envelope, validated for harsh-environment deployment. |
| ID @ VWM | 5 µA - Standby leakage current at rated standoff voltage, ensuring minimal power loss in quiescent systems. |
| αV(BR) | 0.110 %/°C - Temperature coefficient of breakdown voltage, enabling accurate trip-point prediction across thermal extremes. |
Pinout & Package
Package: SQ-MELF (C-package variant), hermetically sealed voidless hard glass with tungsten slugs and tin/lead-plated copper terminals; weight ≈ 1100 mg; dimensions per Microsemi T4-LDS-0278-1 Rev. 2 (BD: 0.183–0.202", BL: 0.205–0.245").
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode/Cathode (bidirectional) | Transient conduction path | No polarity marking - symmetric terminals conduct equally in either direction during overvoltage events. |
| End Cap (both ends) | Thermal interface | Direct thermal path to PCB pads; RθJEC = 5.0 °C/W enables efficient heat dissipation during surge events. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping | Enables single-device protection of AC signals or ungrounded buses without polarity constraints. |
| Category 1 metallurgical bonds | Guarantees bond integrity under thermal cycling and mechanical shock, meeting MIL-PRF-19500/516 reliability requirements. |
| Triple-layer passivation | Prevents moisture ingress and surface leakage, sustaining performance in high-humidity or contaminated environments. |
| Hermetic glass seal | Eliminates internal voids that cause micro-arcing or parameter drift, ensuring long-term parametric stability in mission-critical systems. |
Applications
| Aerospace Power Distribution | Military Data Bus Protection |
|---|---|
Use Scenario: 28 V DC aircraft bus subjected to load dump and lightning-induced surges per DO-160 Section 22. IC Role / Device Role / Timing Role: Primary overvoltage clamp placed directly across bus input to suppress transients before they reach DC-DC converters and avionics modules. Use Value: 245.7 V clamping voltage ensures protected downstream components remain below absolute maximum ratings during 1500 W surges. | Use Scenario: RS-485 data links in armored vehicle command systems exposed to ESD and conducted EFT per MIL-STD-461G CS114. IC Role / Device Role / Timing Role: Bidirectional TVS shunting transient energy on differential pair lines while preserving signal integrity. Use Value: Symmetrical clamping and <5 µA leakage maintain common-mode noise rejection and low standby power in always-on comms nodes. |
| Satellite Power Conditioning | Naval Radar Front-End Protection |
Use Scenario: Solar array regulator inputs in LEO satellites experiencing single-event burnout risks and thermal vacuum cycling. IC Role / Device Role / Timing Role: Radiation-hardened transient suppressor mounted at power entry point to prevent latch-up in PMICs and FPGAs. Use Value: Inherent radiation hardness per MicroNote 050 and –55 °C to +175 °C operation support extended orbital life without derating. | Use Scenario: RF receiver front-end bias lines in shipboard radar systems vulnerable to EMP and antenna-coupled surges. IC Role / Device Role / Timing Role: Low-capacitance TVS protecting GaN amplifier bias rails from fast-rising transients without degrading RF performance. Use Value: Hard-glass construction and Category 1 bonds withstand repeated high-energy pulses without parameter shift or catastrophic failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient voltage suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| JAN1N6171AUS | Lower VWM (121.6 V), lower VC (218.4 V @ 6.9 A), same 1500 W PPP and SQ-MELF package. | Better suited for 115 VAC-derived DC rails where tighter clamping margin is required. | Select when system nominal voltage is ≤120 V and lower clamping headroom is acceptable. |
| JAN1N6173AUS | Higher VWM (152.0 V), higher VC (273.0 V @ 5.5 A), same 1500 W PPP and SQ-MELF package. | Required for 130–150 V DC bus protection where higher standoff prevents false triggering. | Select when protecting >135 V DC systems where 136.8 V VWM would risk conduction during normal operation. |
Compared with JAN1N6172AUS/TR, JAN1N6171AUS offers tighter clamping for mid-voltage rails but reduced standoff margin, while JAN1N6173AUS extends safe operating range to higher DC buses at the cost of elevated clamping voltage-choice depends strictly on system VDC and allowable overvoltage headroom.
Availability
JAN1N6172AUS/TR is available at Aetrix Electronics and suitable for aerospace power distribution, military data bus protection, satellite power conditioning, and naval radar front-end protection requiring stable component supply across extended lifecycle programs.
Supply support for JAN1N6172AUS/TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) designs high-reliability analog and mixed-signal semiconductors for aerospace, defense, and industrial markets, with emphasis on radiation-hardened, high-temperature, and MIL-spec qualified components.
The 1N6138AUS–1N6173AUS family was developed specifically for military-grade transient suppression in mission-critical platforms where failure is not an option, combining hermetic packaging, Category 1 bonding, and IEC/MIL-standard compliance.
FAQ
What is the clamping voltage of JAN1N6172AUS/TR and how is it measured?
The clamping voltage of JAN1N6172AUS/TR is 245.7 V, measured at 6.1 A peak pulse current (IPP) under a standardized 10/1000 µs double-exponential surge waveform. This value reflects the maximum voltage imposed on the protected circuit during transient conduction and is specified in Microsemi's T4-LDS-0278-1 datasheet, Page 3. The test condition ensures repeatability and alignment with IEC61000-4-5 surge immunity testing protocols. JAN1N6172AUS/TR maintains this clamping performance across its full operating temperature range.
Is JAN1N6172AUS/TR RoHS compliant?
No, JAN1N6172AUS/TR is not RoHS compliant. Per Microsemi T4-LDS-0278-1 Rev. 2, RoHS-compliant versions (marked with "e3") are available only for commercial-grade variants-not for JAN-level qualified parts like JAN1N6172AUS/TR. The JAN version uses tin/lead plating on copper terminals and meets MIL-PRF-19500/516 requirements, which permit leaded finishes for high-reliability applications. JAN1N6172AUS/TR is intended for environments where military qualification takes precedence over RoHS restrictions.
What does the "A" suffix in JAN1N6172AUS/TR signify?
The "A" suffix in JAN1N6172AUS/TR indicates standard voltage tolerance: ±5% on V(BR), ±5% on VC, and ±5% on IPP, as defined in the nomenclature section of Microsemi's T4-LDS-0278-1 datasheet. Non-A versions have looser tolerances-5% higher VC, 5% lower minimum V(BR), and 5% lower IPP-which reduce design margin. JAN1N6172AUS/TR therefore guarantees tighter parametric control essential for precision overvoltage protection in safety-critical systems.
Can JAN1N6172AUS/TR be used in place of axial-leaded 1N6172 parts?
No, JAN1N6172AUS/TR is not a direct replacement for axial-leaded 1N6172 parts due to fundamental package differences: JAN1N6172AUS/TR uses a surface-mount SQ-MELF (C-package) configuration, while axial-leaded versions use through-hole TO-204AA (DO-41) construction. Mounting, thermal path, and board layout are incompatible. Although electrical parameters match, mechanical integration requires redesign. JAN1N6172AUS/TR must be placed on SMT pads per the pad layout in T4-LDS-0278-1 Page 7-not substituted into through-hole footprints.
What is the maximum steady-state power dissipation for JAN1N6172AUS/TR at 25 °C ambient?
The maximum steady-state power dissipation for JAN1N6172AUS/TR is 3.0 W at TA = 25 °C, as specified in the "Off-State Power @ TA = 25 °C" row of the Maximum Ratings table (T4-LDS-0278-1 Page 1). This rating assumes adequate PCB thermal management-derating begins linearly above 25 °C ambient, reaching zero at 150 °C case temperature. JAN1N6172AUS/TR is not intended for continuous power regulation; its primary function remains transient suppression, not DC power handling.
JAN1N6172AUS/TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- SQ-MELF, C
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 136.8V
- Voltage - Breakdown (Min):
- 171V
- Voltage - Clamping (Max) @ Ipp:
- 245.7V
- Current - Peak Pulse (10/1000µs):
- 6.1A
- Power - Peak Pulse:
- 1500W (1.5kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 175°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500/516
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- C, SQ-MELF
JAN1N6172AUS/TR FAQ
1.How can I place an order for JAN1N6172AUS/TR through Aetrix?
Please submit a Request for Quotation (RFQ) for JAN1N6172AUS/TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for JAN1N6172AUS/TR reliable?
The price and inventory of JAN1N6172AUS/TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for JAN1N6172AUS/TR is usually 5 days.
3.What payment methods are accepted for JAN1N6172AUS/TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for JAN1N6172AUS/TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for JAN1N6172AUS/TR?
JAN1N6172AUS/TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your JAN1N6172AUS/TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for JAN1N6172AUS/TR?
For technical support, including JAN1N6172AUS/TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your JAN1N6172AUS/TR requirements.
6.How does Aetrix verify that JAN1N6172AUS/TR is sourced from the original manufacturer or authorized distributors?
All JAN1N6172AUS/TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that JAN1N6172AUS/TR meets industry standards.
7.What is the process for return or replacement of JAN1N6172AUS/TR?
All JAN1N6172AUS/TR units undergo pre-shipment inspection (PSI). If there is an issue with JAN1N6172AUS/TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The JAN1N6172AUS/TR part is unused and in its original packaging.
Return procedure for JAN1N6172AUS/TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
JAN1N6172AUS/TR Tags
-
ESD9B5.0ST5G
onsemi
-
DESD3V3E1BL-7B
Diodes Incorporated
-
ESD5Z3.3T1G
onsemi
-
D5V0H1B2LP-7B
Diodes Incorporated
-
D5V0P1B2LP-7B
Diodes Incorporated
-
DESD5V0U1BA-7
Diodes Incorporated
-
ESD5Z5.0T1G
onsemi
-
DESD5V0U1BB-7
Diodes Incorporated
-
D12V0L1B2LP-7B
Diodes Incorporated
-
PESD2V0Y1BSFYL
Nexperia USA Inc.
-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage
-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
