My Inquiry
My Account
STMicroelectronics LIS2DUXS12TR
- Part No.:
- LIS2DUXS12TR
- Manufacturer:
- STMicroelectronics
- Category:
- Accelerometers
- Package:
- 12-WFLGA
- Datasheet:
-
LIS2DUXS12TR.pdf
- Description:
- ULTRALOW-POWER ACCELEROMETER WIT
- Quantity:
- Payment:
- Shipping:
Inventory:9,097
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LIS2DUXS12TR from STMicroelectronics is a smart 3-axis digital accelerometer with integrated machine learning core (MLC), finite state machine (FSM), analog hub/Qvar sensing channel, and antialiasing filter. It operates from 1.62 V to 3.6 V (Vdd), supports ±2g/±4g/±8g/±16g full-scale, delivers 220 µg/√Hz noise density in high-performance mode, and achieves ultralow 3 µA supply current in ultralow-power mode - enabling always-on motion intelligence in compact wearable devices.
For engineers reviewing the LIS2DUXS12TR datasheet, LIS2DUXS12TR pinout, LIS2DUXS12TR application, or LIS2DUXS12TR equivalent, key selection criteria include its MIPI I3C® interface support, 128-sample embedded FIFO, adaptive self-configuration (ASC) driven by FSM/MLC outputs, Qvar electrode capability for capacitive sensing, and dual interrupt pins (INT1/INT2) configurable as AH inputs - all critical for edge AI sensor nodes and ultra-low-power human interface design.
Technical Context
The LIS2DUXS12TR implements a cascaded signal chain: mechanical MEMS elements feed an analog antialiasing low-pass filter (enabled only in high-performance and low-power modes), followed by a 16-bit ADC and programmable digital LPF1. Its embedded MLC executes trained neural network models directly on sensor data, while the FSM runs user-defined state transitions - both trigger ASC to dynamically reconfigure sensor parameters (ODR, full-scale, filtering) based on real-time output.
It features three independent power domains: Vdd (core logic & MEMS), Vdd_IO (I²C/SPI), and extended-range Vdd_IO (1.08–3.6 V) for MIPI I3C®. The analog hub provides two dedicated Qvar input channels (AH_QVAR1/AH_QVAR2 mapped to INT1/INT2), supporting capacitive sensing with 1100 MΩ input impedance (configurable) and 510 µVRMS noise at gain = 2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage (Vdd) | 1.62 V to 3.6 V - enables direct integration with 1.8 V or 3.3 V system rails without level-shifting. |
| Output data rate (ODR) | 1.6 Hz to 800 Hz - supports both slow-motion tracking (e.g., tilt detection) and fast gesture recognition (e.g., triple-tap). |
| Noise density | 220 µg/√Hz - ensures high-resolution motion capture for pedometer accuracy and subtle activity classification. |
| FIFO depth | 128 samples (accel + temp / Qvar) or 256 samples (accel only, low-res) - reduces host MCU polling frequency and burst-read overhead. |
| Shock survivability | 10000 g - guarantees robustness in portable consumer electronics subjected to drops and impacts. |
| Operating temperature | −40 °C to +85 °C - validated for use in wrist-worn wearables and industrial edge sensors without thermal derating. |
| Interface support | I²C (up to 1 MHz), SPI (10 MHz), MIPI I3C® (12.5 MHz) - allows flexible host connectivity including multi-sensor synchronization via I3C broadcast commands. |
Pinout & Package
Package: LGA-12L, 2.0 mm × 2.0 mm × 0.74 mm (max), RoHS-compliant, land grid array with exposed pad for thermal and electrical grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SCL/SPC) | Serial clock input | Shared I²C SCL / SPI SPC - enables dual-interface hardware reuse; requires external pull-up for I²C operation. |
| 2 (CS) | Interface mode select | Active-low SPI enable; pulled up internally - drives I²C/I3C when high, SPI when low. |
| 3 (SDO/SA0) | Data output / address bit | SPI SDO output or I²C SA0 (LSB of 7-bit address); internal pull-up disabled by default. |
| 4 (SDA/SDI/SDO) | Bidirectional data | I²C/SDA, SPI/SDI, or 3-wire SDO - supports tri-state control for bus sharing. |
| 5 (NC) | No connect | Internally unconnected; may be tied to Vdd, Vdd_IO, or GND per layout requirements. |
| 6 & 8 (GND) | Ground reference | Dual GND pins improve return path integrity and reduce ground bounce in high-speed digital interfaces. |
| 7 (RES/EXT_CLK) | Reset / external clock | Configurable as active-low reset or synchronization clock input for multi-sensor timing alignment. |
| 9 (Vdd) | Core supply | Powers MEMS sensor, ASIC logic, and internal regulators - must be decoupled near package. |
| 10 (Vdd_IO) | I/O supply | Independent rail for digital interfaces; supports 1.08–3.6 V (I3C) or 1.62–3.6 V (I²C/SPI) - enables mixed-voltage system interfacing. |
| 11 (INT2) | Interrupt 2 / AH input 2 | Programmable interrupt output or second Qvar electrode input - dual-role pin enables compact capacitive sensing designs. |
| 12 (INT1) | Interrupt 1 / AH input 1 | Primary interrupt output or first Qvar electrode input - supports simultaneous motion + capacitive event detection. |
Key Features
| Feature | Design Value |
|---|---|
| Embedded machine learning core (MLC) | Executes trained neural networks on-device - eliminates cloud dependency and reduces latency for gesture classification and anomaly detection. |
| Adaptive self-configuration (ASC) | Automatically adjusts ODR, full-scale, and filtering based on MLC/FSM output - extends battery life without sacrificing responsiveness. |
| Qvar analog hub | Two dedicated capacitive sensing inputs (INT1/INT2) with programmable gain and 1100 MΩ input impedance - enables touchless UI, proximity, or moisture sensing alongside motion. |
| Always-on antialiasing filter | Hardware analog LPF enabled in HP/LP modes - prevents aliasing at max ODR (800 Hz) without CPU intervention or firmware overhead. |
| 128-level FIFO with flexible buffering | Stores mixed-data packets (accel, temp, Qvar) - allows host MCU to read batches infrequently, minimizing wake-ups and system power consumption. |
Applications
| Wearable Motion Intelligence | Capacitive + Motion Hybrid Sensing |
|---|---|
Use Scenario: Continuous step counting, fall detection, and screen rotation in smartwatches and fitness bands. IC Role / Device Role / Timing Role: Primary 3-axis motion sensor with embedded pedometer, tilt detection, and 6D orientation engine - operates autonomously in ultralow-power mode (3 µA). Use Value: Eliminates need for external motion coprocessor; ASC dynamically scales ODR from 1.6 Hz (idle) to 800 Hz (gesture) to optimize power vs. responsiveness. | Use Scenario: Touchless gesture control and proximity sensing in true wireless stereo earbuds. IC Role / Device Role / Timing Role: Dual-role device: accelerometer for tap/double-tap detection and Qvar electrodes (INT1/INT2) for ear detection and swipe gestures. Use Value: Single-chip solution replaces separate motion + capacitive sensors - saves PCB area and simplifies calibration across sensing modalities. |
| Industrial Asset Tracking | Healthcare Motion Monitoring |
Use Scenario: Shock/vibration logging and tamper detection in logistics trackers deployed in harsh environments. IC Role / Device Role / Timing Role: High-shock survivability (10000 g) accelerometer with wake-up interrupt triggered by impact events - initiates GPS/Wi-Fi reporting only on motion. Use Value: Extends battery life to multi-year operation by keeping host MCU in deep sleep until validated motion event occurs. | Use Scenario: Fall risk assessment and gait analysis in portable hearing aids and remote patient monitors. IC Role / Device Role / Timing Role: Low-noise (220 µg/√Hz) motion sensor with embedded temperature compensation and factory-calibrated offset (±30 mg) - ensures clinical-grade repeatability. Use Value: Delivers consistent motion metrics across temperature variations (-40 °C to +85 °C), critical for longitudinal health data validity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar smart accelerometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LSM6DSO32XTR | Higher current (150 µA HP mode), no Qvar hub, includes gyroscope - lacks capacitive sensing capability. | Targeted at IMU-based VR/AR where angular motion matters more than capacitive interaction. | Select when 6DoF fusion is required and Qvar functionality is unnecessary. |
| BMI270 | Lower noise (115 µg/√Hz), no MLC (only basic FSM), no analog hub - limited edge AI capability. | Suitable for cost-sensitive wearables needing high-precision motion but no adaptive configuration or capacitive sensing. | Choose for pure motion accuracy without ASC or hybrid sensing requirements. |
Compared with LSM6DSO32XTR and BMI270, the LIS2DUXS12TR uniquely integrates Qvar sensing, ASC-driven power optimization, and MLC-based inference - making it the only option among the three capable of autonomous, multi-modal (motion + capacitance) edge intelligence in sub-10 µA systems.
Availability
LIS2DUXS12TR is available at Aetrix Electronics and suitable for wearable devices, true wireless stereo earbuds, and industrial asset trackers requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for LIS2DUXS12TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, sensors, power ICs, and automotive semiconductors since 1987.
The LIS2DUXS12TR belongs to ST's "smart sensor" product line, engineered specifically for ultra-low-power, AI-enabled edge sensing in space-constrained portable electronics - emphasizing on-device intelligence, multi-function integration, and seamless host interface flexibility.
FAQ
What is the function of the RES/EXT_CLK pin on the LIS2DUXS12TR?
The RES/EXT_CLK pin serves dual roles: as an active-low reset input when configured in reset mode, or as an external clock input for synchronizing multiple LIS2DUXS12TR sensors in a distributed system. When used for synchronization, the EXT_CLK_EN bit in register EXT_CLK_CFG (08h) must be set, and INT1_ON_RES in CTRL1 (10h) cleared to avoid conflict with interrupt routing.
How does the adaptive self-configuration (ASC) feature operate in practice?
ASC dynamically modifies sensor parameters - such as ODR, full-scale range, and filtering - based on real-time outputs from the FSM or MLC. For example, if the MLC detects walking, ASC can increase ODR from 12.5 Hz to 200 Hz and switch to ±4g full-scale; if idle is recognized, it scales down to 1.6 Hz and ±2g to minimize current draw - all without host MCU intervention.
Can the INT1 and INT2 pins be used simultaneously for interrupts and Qvar sensing?
No - each of INT1 and INT2 operates in one mode at a time: either as a programmable interrupt output (free-fall, tap, activity) or as an analog input for the Qvar sensing channel. Configuration is controlled via the AH_QVAR_EN bit in register CTRL10_C (19h); enabling Qvar disables interrupt generation on that pin.
What is the maximum supported clock frequency for the MIPI I3C® interface on the LIS2DUXS12TR?
The LIS2DUXS12TR supports MIPI I3C® up to 12.5 MHz in high-data-rate (HDR) mode, with backward compatibility to I²C fast-mode-plus (1 MHz). Its extended Vdd_IO range (1.08 V to 3.6 V) allows direct interfacing with 1.2 V I3C masters without level shifters - verified per MIPI I3C v1.1 specification.
LIS2DUXS12TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 12-WFLGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Digital
- Axis:
- X, Y, Z
- Acceleration Range:
- ±2g, 4g, 8g, 16g
- Sensitivity (LSB/g):
- 16393 (±2g) ~ 2049 (±16g)
- Sensitivity (mV/g):
- -
- Bandwidth:
- 0.8Hz ~ 400Hz
- Output Type:
- -
- Voltage - Supply:
- -
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-LGA (2x2)
LIS2DUXS12TR FAQ
1.How can I place an order for LIS2DUXS12TR through Aetrix?
Please submit a Request for Quotation (RFQ) for LIS2DUXS12TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LIS2DUXS12TR reliable?
The price and inventory of LIS2DUXS12TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LIS2DUXS12TR is usually 5 days.
3.What payment methods are accepted for LIS2DUXS12TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LIS2DUXS12TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LIS2DUXS12TR?
LIS2DUXS12TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LIS2DUXS12TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LIS2DUXS12TR?
For technical support, including LIS2DUXS12TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LIS2DUXS12TR requirements.
6.How does Aetrix verify that LIS2DUXS12TR is sourced from the original manufacturer or authorized distributors?
All LIS2DUXS12TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LIS2DUXS12TR meets industry standards.
7.What is the process for return or replacement of LIS2DUXS12TR?
All LIS2DUXS12TR units undergo pre-shipment inspection (PSI). If there is an issue with LIS2DUXS12TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LIS2DUXS12TR part is unused and in its original packaging.
Return procedure for LIS2DUXS12TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LIS2DUXS12TR Tags
-
MXC4005XC
Memsic Inc.
-
MC3419
Memsic Inc.
-
MC3479
Memsic Inc.
-
MXC6655XA
Memsic Inc.
-
MC3630
Memsic Inc.
.jpg)
-
LIS2HH12TR
STMicroelectronics
-
KX122-1037
Kionix Inc.
-
LIS2DE12TR
STMicroelectronics
-
LIS2DH12TR
STMicroelectronics
-
MC3635
Memsic Inc.
-
LIS2DS12TR
STMicroelectronics
-
LIS3DHTR
STMicroelectronics
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
