STMicroelectronics M24SR02-YDW6T/2

Overview

M24SR02-YDW6T/2 from STMicroelectronics is a dynamic NFC/RFID tag IC with dual I²C and contactless interfaces, embedding 2-Kbit EEPROM compliant with NFC Forum Type 4 Tag and ISO/IEC 14443 Type A. It operates from 2.7 V to 5.5 V, supports 1 MHz I²C, delivers 106 Kbps RF data rate, and features 7-byte UID and 128-bit password protection. Used in secure product authentication and smart packaging where NFC-enabled mobile interaction meets embedded microcontroller control.

For engineers reviewing the M24SR02-YDW6T/2 datasheet, M24SR02-YDW6T/2 pinout, M24SR02-YDW6T/2 application, or M24SR02-YDW6T/2 equivalent, key selection criteria include dual-interface session arbitration, NDEF file management with password-protected access rights, GPO-configurable status signaling, RF disable control, and compatibility with industrial temperature range (–40 °C to +85 °C) designs.

Technical Context

The device implements concurrent I²C slave and ISO/IEC 14443-A RF tag functionality with hardware-level session arbitration: an active RF session blocks I²C access until closed, and vice versa. Its memory architecture includes dedicated CC (Capability Container), NDEF, and System files, all supporting NDEF data structure per NFC Forum specifications.

RF interface integrates internal 25 pF tuning capacitance for antenna matching and supports anticollision, RATS/ATS, and PPS protocols. I²C interface uses standard two-wire protocol with configurable slave address, ACK/NACK handshaking, and timeout detection on clock stretching - enabling robust integration into host MCU systems without dedicated NFC controllers.

Key Specifications

Pinout & Package

Available in three ECOPACK2-compliant packages: SO8 (small-outline), TSSOP8 (thin shrink small-outline), and UFDFPN8 (ultra-thin fine-pitch no-lead). Pin functions are identical across variants.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dynamic NFC tag applications.

Compared with NT3H2111W0FHKH, M24SR02-YDW6T/2 provides essential I²C control for embedded systems; compared with M24SR64-YDW6T/2, it offers optimal cost/performance balance for compact NDEF use cases like authentication tokens and simple configuration tags.

Availability

M24SR02-YDW6T/2 is available at Aetrix Electronics and suitable for smart packaging, industrial asset tagging, and consumer electronics pairing requiring stable component supply, full production status since April 2019, and long-term lifecycle commitment.

Supply support for M24SR02-YDW6T/2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, sensors, and connectivity solutions for industrial, automotive, and consumer markets.

The M24SR series belongs to ST's ST25 NFC/RFID platform, designed specifically for secure dual-interface tagging in applications demanding both smartphone accessibility and embedded system control - bridging physical products and digital services.

FAQ

What is the function of the RF Disable pin?

The RF Disable pin is an active-low hardware control that disables the RF interface independently of I²C activity. When asserted, it prevents RF field detection and communication, eliminating unintended tag activation during I²C programming or system sleep modes. This feature ensures deterministic interface control without relying on software commands, improving system reliability in noise-prone environments.

How does session arbitration work between I²C and RF interfaces?

Session arbitration is implemented in hardware: initiating an RF session automatically blocks I²C access until the RF session closes, and vice versa. The device uses token-based session management - each interface must acquire its respective token before accessing memory. This prevents race conditions and memory corruption, eliminating the need for external coordination logic or software locks in dual-access architectures.

Can the GPO pin indicate multiple simultaneous events?

No - the GPO pin reflects only one configured event state at a time, selected via the GPO field in the System file (e.g., 0x11 for Session Open, 0x22 for WIP). Multiple events require sequential polling or use of the INT configuration (GPO field = 0x4X), which asserts the pin on any enabled interrupt condition and clears only after host reads the corresponding status register - enabling edge-triggered notification without continuous polling.

What NDEF file structures are supported, and how is access controlled?

The device supports standard NFC Forum-defined CC (Capability Container), NDEF, and System files. Access rights are enforced per-file using 128-bit passwords stored in the System file: separate keys govern read and write permissions, and access lifetime can be set to "permanent" or "session-only." Passwords are verified via ISO/IEC 7816-4 Verify commands, and file locking/unlocking follows strict procedural sequences documented in Section 8 of the datasheet.