STMicroelectronics M24SR64-YDW6T/2
- Part No.:
- M24SR64-YDW6T/2
- Manufacturer:
- STMicroelectronics
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- 8-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
M24SR64-YDW6T/2.pdf
- Description:
- IC RFID TRANSP 13.56MHZ 8TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:19,783
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Product details
Overview
M24SR64-YDW6T/2 from STMicroelectronics is a dynamic NFC/RFID tag IC with dual-interface operation (I²C + 13.56 MHz RF), 64-Kbit EEPROM, NFC Forum Type 4 Tag compliance, ISO/IEC 14443 Type A support, and 7-byte UID - used in secure access control systems, smart packaging, and industrial asset tagging where contactless data exchange and local I²C host control coexist.
For engineers reviewing the M24SR64-YDW6T/2 datasheet, M24SR64-YDW6T/2 pinout, M24SR64-YDW6T/2 application, or M24SR64-YDW6T/2 equivalent, this page delivers verified functional modes (I²C slave, RF tag, dual-session arbitration), memory endurance specs (1M cycles @25°C), GPO configuration options, UID uniqueness, and real-world NDEF file handling behavior - all critical for NFC-enabled embedded system integration.
Technical Context
The M24SR64-YDW6T/2 implements concurrent I²C and RF interfaces with session arbitration logic: an active I²C session disables RF commands until explicitly released, while RF sessions pause I²C access during tag interrogation. It supports full NFC Forum Type 4 Tag protocol stack including CC and NDEF file structures, with ISO/IEC 7816-4–compliant authentication commands (Verify, Change Reference Data).
Its dual-interface architecture enables deterministic state transitions between I²C mode (slave address 0x50), RF mode (Type A, 106 kbps), and dual-interface mode where host MCU writes data via I²C and end-user reads it via NFC phone - with hardware-level RF disable control and configurable GPO signaling for session status (e.g., WIP, INT, RF busy).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory capacity | 64-Kbit (8-Kbyte) EEPROM with NDEF data structure support - enables storage of multiple NDEF records (e.g., URLs, text, smart posters) in standardized format readable by NFC smartphones. |
| I²C interface | Two-wire slave interface up to 1 MHz - compatible with standard microcontroller I²C peripherals; uses fixed 7-bit address 0x50 and supports repeated start conditions for multi-byte transfers. |
| RF interface | NFC Forum Type 4 Tag compliant, ISO/IEC 14443 Type A, 106 kbps - interoperable with Android/iOS NFC readers without custom driver development. |
| Data retention | 200 years at 25 °C - ensures long-term integrity of stored credentials, calibration data, or firmware metadata in industrial or medical devices. |
| Write endurance | 1 million cycles at 25 °C; 600k at 85 °C; 500k at 105 °C - supports frequent field-updatable parameters in automotive telematics or IoT sensor nodes. |
| Unique identifier | 7-byte UID factory-programmed and read-only - provides cryptographic binding for device identity in secure boot or anti-counterfeiting applications. |
| Supply voltage | 2.7 V to 5.5 V single supply - simplifies power design across 3.3 V and 5 V embedded systems without level-shifting. |
Pinout & Package
Package: 8-lead TSSOP8 (ECOPACK2®), SO8, or UFDFPN8 - surface-mount compatible with automated PCB assembly; thermal and mechanical characteristics validated per JEDEC standards for industrial temperature operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SCL | I²C clock input | Bidirectional clock line synchronized to host controller; internal pull-up not provided - requires external 2.2–10 kΩ pull-up resistor. |
| SDA | I²C data bidirectional | Open-drain I²C data line; shares bus with other I²C slaves; supports standard and fast-mode protocols. |
| VCC | Power supply | Single 2.7–5.5 V supply powering both I²C logic and RF analog front-end; decoupling capacitor (100 nF) required near pin. |
| VSS | Ground reference | Digital and RF ground plane connection; must be low-impedance and tied to system common ground. |
| AC0 / AC1 | RF antenna terminals | Differential 13.56 MHz RF interface; connects directly to printed loop antenna or discrete coil; internal 25 pF tuning capacitance reduces external component count. |
| GPO | Configurable general-purpose output | Programmable open-drain output signaling RF/I²C session states (e.g., WIP, INT, RF busy); driven only when enabled in System File. |
| RF Disable | RF interface enable/disable control | Active-low digital input disabling RF receiver path - allows host MCU to prevent unintended tag activation during I²C programming. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-interface session arbitration | Hardware-enforced mutual exclusion between I²C and RF access prevents memory corruption during concurrent host/NFC reader operations. |
| NDEF file password protection | 128-bit password per NDEF file - enables selective read/write access control for multi-application use cases (e.g., public URL + private diagnostics data). |
| I²C watchdog timeout | Configurable I²C session timeout (default 100 ms) - automatically releases I²C token on bus hang, preventing RF lockout in unresponsive host scenarios. |
| RF disable pin | Dedicated hardware control to disable RF interface independently of power state - essential for EMI-sensitive environments or battery-powered devices requiring zero RF leakage. |
| GPO state signaling | Seven programmable GPO configurations (e.g., Session Open, WIP, I²C answer ready) - eliminates need for polling and reduces host CPU overhead in real-time systems. |
Applications
| Smart Access Credentials | Industrial Asset Tagging |
|---|---|
Use Scenario: Embedded in door lock PCBs or badge holders to store encrypted access keys and user permissions. IC Role / Device Role / Timing Role: Dual-interface tag IC providing secure credential storage accessible via I²C during enrollment and via NFC smartphone during authentication. Use Value: Enables offline credential validation without cloud dependency; UID and password protection prevent cloning or unauthorized overwrite. |
Use Scenario: Mounted on factory equipment to store maintenance logs, calibration history, and firmware version. IC Role / Device Role / Timing Role: Nonvolatile memory node supporting both local MCU updates (I²C) and technician field verification (NFC phone scan). Use Value: Eliminates manual logbooks; 200-year data retention ensures traceability over equipment lifetime; RF disable prevents accidental reprogramming on shop floor. |
| Secure Smart Packaging | Medical Device Authentication |
Use Scenario: Integrated into pharmaceutical blister packs or diagnostic kit labels to verify authenticity and track batch information. IC Role / Device Role / Timing Role: Tamper-evident NFC tag storing encrypted NDEF records readable by pharmacy scanners and consumer phones. Use Value: Prevents counterfeit distribution using UID+password binding; write endurance supports batch-specific data injection during packaging line operation. |
Use Scenario: Embedded in reusable surgical instruments to log sterilization cycles and usage counts. IC Role / Device Role / Timing Role: High-reliability memory element retaining critical lifecycle data across repeated autoclave cycles (105 °C ambient). Use Value: Meets IEC 62304 software safety requirements; 500k write cycles at 105 °C ensure data integrity in high-temp medical environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dynamic NFC tag applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXH3670UK | Integrated NFC controller + secure element; no EEPROM; requires external flash for NDEF storage. | Targeted at mobile payment and secure transaction use cases, not standalone tag replacement. | Select when cryptographic key management and EMVCo compliance are required over local data storage. |
| M24SR16-YDW6T/2 | Same architecture and pinout, but 16-Kbit (2-Kbyte) EEPROM capacity. | Lower-cost option for simple NDEF payloads (e.g., single URL, short text) with identical RF/I²C timing and security features. | Select when memory requirement is ≤2 Kbytes and BOM cost optimization is prioritized. |
Compared with NXH3670UK, M24SR64-YDW6T/2 offers self-contained NDEF storage without external memory, while versus M24SR16-YDW6T/2, it provides 4× more EEPROM space for complex multi-record applications - making it optimal for industrial and medical use cases demanding both capacity and proven reliability.
Availability
M24SR64-YDW6T/2 is available at Aetrix Electronics and suitable for secure access control systems, industrial asset tagging, and medical device authentication requiring stable component supply, long-term data retention, and dual-interface flexibility.
Supply support for M24SR64-YDW6T/2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, sensors, and connectivity solutions - with broad industrial, automotive, and consumer market reach.
The M24SR64-YDW6T/2 belongs to the ST25 NFC/RFID product line, designed specifically for secure, dual-interface data exchange in resource-constrained embedded systems where tamper resistance, long-term memory reliability, and NFC interoperability are mandatory.
FAQ
What is the default I²C slave address for M24SR64-YDW6T/2?
The fixed 7-bit I²C slave address is 0x50 (1010000b), with R/W bit appended externally by the host controller. This address is hard-coded and non-configurable, ensuring predictable bus enumeration in multi-slave systems without address conflict risk.
How does the RF disable pin function during I²C operation?
The RF Disable pin is an active-low input that permanently disables the RF receiver path when pulled low, regardless of I²C session state. It remains effective even during power-up reset and allows deterministic RF suppression in EMI-critical zones or battery-saving modes.
Can the GPO pin signal both I²C and RF events simultaneously?
No - GPO is configured for one event type at a time via the System File's GPO field (e.g., 0x11 for Session Open, 0x22 for WIP). It cannot multiplex signals; however, rapid reconfiguration under host control enables sequential notification of different interface states.
What is the maximum NDEF message size supported in a single read command?
The M24SR64-YDW6T/2 supports reading up to 246 bytes in a single ReadBinary command, constrained by the I²C frame buffer and RF block size limits. Larger NDEF messages require segmented reads, with each segment aligned to 256-byte boundaries per the NFC Forum Type 4 specification.
M24SR64-YDW6T/2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- RFID Transponder
- Frequency:
- 13.56MHz
- Standards:
- ISO 14443, NFC
- Interface:
- I2C
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
M24SR64-YDW6T/2 FAQ
1.How can I place an order for M24SR64-YDW6T/2 through Aetrix?
Please submit a Request for Quotation (RFQ) for M24SR64-YDW6T/2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for M24SR64-YDW6T/2 reliable?
The price and inventory of M24SR64-YDW6T/2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for M24SR64-YDW6T/2 is usually 5 days.
3.What payment methods are accepted for M24SR64-YDW6T/2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for M24SR64-YDW6T/2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for M24SR64-YDW6T/2?
M24SR64-YDW6T/2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your M24SR64-YDW6T/2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for M24SR64-YDW6T/2?
For technical support, including M24SR64-YDW6T/2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your M24SR64-YDW6T/2 requirements.
6.How does Aetrix verify that M24SR64-YDW6T/2 is sourced from the original manufacturer or authorized distributors?
All M24SR64-YDW6T/2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that M24SR64-YDW6T/2 meets industry standards.
7.What is the process for return or replacement of M24SR64-YDW6T/2?
All M24SR64-YDW6T/2 units undergo pre-shipment inspection (PSI). If there is an issue with M24SR64-YDW6T/2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The M24SR64-YDW6T/2 part is unused and in its original packaging.
Return procedure for M24SR64-YDW6T/2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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