Microchip Technology MAPLAD18KP110CAE3
- Part No.:
- MAPLAD18KP110CAE3
- Manufacturer:
- Microchip Technology
- Category:
- TVS Diodes
- Package:
- Nonstandard SMD
- Datasheet:
-
MAPLAD18KP110CAE3.pdf
- Description:
- TVS DIODE 110VWM 177VC PLAD
- Quantity:
- Payment:

- Shipping:

Inventory:3,148
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Product details
Overview
MAPLAD18KP110CAE3 from Microsemi is a bidirectional surface-mount transient voltage suppressor (TVS) rated for 18,000 W peak pulse power at 10/1000 μs, with 110 V reverse standoff voltage (VWM), 122–135 V breakdown voltage (V(BR)), and 177 A peak pulse current (IPP). It delivers low-clamping performance (VC = 177 V max @ IPP) and meets RTCA DO-160 Section 22 multi-stroke lightning protection requirements in aerospace systems.
For engineers reviewing the MAPLAD18KP110CAE3 datasheet, MAPLAD18KP110CAE3 pinout, MAPLAD18KP110CAE3 application, or MAPLAD18KP110CAE3 equivalent, this device is selected for high-reliability secondary lightning protection, automotive load dump suppression, and ESD/EFT immunity in avionics power rails where thermal resistance (RθJC = 0.7 °C/W) and RoHS-compliant packaging are critical.
Technical Context
The MAPLAD18KP110CAE3 is a silicon avalanche diode-based TVS designed for bidirectional clamping across DC power lines. Its metal-base package enables direct thermal coupling to heatsinks, supporting sustained surge handling under ≤0.05% duty cycle per Figure 2. The device operates over –55°C to +150°C junction temperature and complies with IEC 61000-4-2 (ESD), IEC 61000-4-4 (EFT), and IEC 61000-4-5 (lightning) with 42 Ω, 12 Ω, and 2 Ω source impedances.
It features a low-profile void-free UL94V-0 epoxy body, matte-tin RoHS-compliant terminations (e3), and polarity marking indicating cathode on the metal base. Standby current ID is ≤10 μA at VWM, and clamping response time is <5 ns - validated per RTCA/DO-160F Waveform 4 and 5A pin-injection testing up to Level 5 (for VWM ≤130 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Pulse Power (PPP) | 18,000 W @ 10/1000 μs - sustains aircraft lightning transients without failure |
| Reverse Standoff Voltage (VWM) | 110 V - sets maximum continuous operating voltage before clamping initiates |
| Breakdown Voltage (V(BR)) | 122–135 V @ I(BR) - defines guaranteed avalanche conduction threshold |
| Max Clamping Voltage (VC) | 177 V @ IPP = 177 A - limits downstream voltage stress during surge events |
| Junction-to-Case Thermal Resistance | 0.7 °C/W - enables efficient heat transfer to PCB copper or external heatsink |
| Standby Current (ID) | ≤10 μA @ VWM - ensures negligible leakage in standby power rails |
| Clamping Response Time | <5 ns - provides sub-nanosecond reaction to fast-rising transients |
Pinout & Package
MAPLAD18KP110CAE3 uses a surface-mount PLAD (Power Leadless Array Diode) package with a metal base acting as the cathode terminal for bidirectional operation. The package measures 12.32 × 10.54 × 3.68 mm (L × W × H), with solderable matte-tin terminations conforming to MIL-STD-750 Method 2026.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Metal Base (Bottom) | Cathode (Bidirectional Common Terminal) | Serves as primary thermal path and electrical return; must be soldered to large copper pour or heatsink |
| Top Surface Pad | Anode (Bidirectional Common Terminal) | Provides symmetrical clamping between line and ground; no polarity sensitivity in circuit layout |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping architecture | Enables symmetric transient suppression on AC-coupled or floating DC buses without polarity constraints |
| 0.7 °C/W RθJC | Allows >10× higher thermal power dissipation vs. standard SMD TVS, enabling repeated surge endurance |
| RTCA DO-160F Waveform 4 & 5A compliance | Validated for Level 4 (≤200 V) and Level 5 (≤130 V) pin-injection immunity - directly applicable to MAPLAD18KP110CAE3 |
| IEC 61000-4-5 Class 1–5 support (42 Ω Zs) | Meets full secondary lightning protection scope for avionics power inputs without external conditioning |
| Moisture Sensitivity Level 1 | Eliminates dry-pack requirement and floor-life limitations - simplifies SMT assembly logistics |
Applications
| Aerospace Power Distribution | Automotive Load Dump Protection |
|---|---|
Use Scenario: 28 V DC distribution bus in commercial aircraft avionics racks exposed to multi-stroke lightning per DO-160 Section 22. IC Role / Device Role / Timing Role: Bidirectional TVS placed at power entry point to clamp induced surges before reaching DC-DC converters and flight control modules. Use Value: 18 kW PPP rating and <5 ns response ensure system-level compliance without derating or parallel devices. | Use Scenario: 12 V/24 V battery-fed ECUs in heavy-duty vehicles subjected to ISO 16750-2 load dump transients up to 120 V. IC Role / Device Role / Timing Role: Primary surge protector across battery input, absorbing energy before upstream fuses open or downstream regulators fail. Use Value: 110 V VWM matches nominal 28 V system headroom while clamping at 177 V - safely within 36 V automotive semiconductor limits. |
| Industrial Motor Drive DC Bus | Railway Signaling Interface |
Use Scenario: DC link of 400 V industrial VFDs experiencing switching-induced transients from IGBT commutation and regenerative braking. IC Role / Device Role / Timing Role: Secondary protection stage after bulk MOVs, providing precise clamping and fast recovery for sensitive gate drivers. Use Value: Low RθJC enables mounting directly to aluminum chassis, reducing thermal interface layers and improving long-term reliability under repetitive surges. | Use Scenario: 110 V signaling lines in European railway interlocking systems requiring EN 50121-3-2 surge immunity up to Class 4 (2 kV, 42 Ω Zs). IC Role / Device Role / Timing Role: Line-to-ground TVS on trackside signal inputs to protect FPGA-based logic controllers from induced lightning currents. Use Value: 110 V VWM aligns precisely with nominal signaling voltage, minimizing false triggering while maintaining margin for 20% overvoltage tolerance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar transient voltage suppression applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMBJ110CA | 600 W PPP rating, SMA package, RθJC ≈ 40 °C/W | Limited to single-stroke or low-duty-cycle surges; unsuitable for DO-160 multi-stroke validation | Select only for cost-sensitive industrial controls with verified low-energy threat profiles |
| SMCJ110CA | 1500 W PPP, SMC package, RθJC ≈ 10 °C/W, no DO-160 qualification | Requires larger PCB area and thermal relief; lacks aerospace screening traceability | Use where MIL-PRF-19500 upscreening and lot traceability are not required |
Compared with SMBJ110CA and SMCJ110CA, MAPLAD18KP110CAE3 delivers 30× higher peak power handling, 14× lower thermal resistance, and certified DO-160F/IEC 61000-4-5 compliance - making it the sole option for mission-critical aerospace and high-reliability rail applications demanding repeatable 18 kW surge absorption.
Availability
MAPLAD18KP110CAE3 is available at Aetrix Electronics and suitable for aerospace power distribution, automotive load dump protection, and industrial motor drive DC bus applications requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for MAPLAD18KP110CAE3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microsemi Corporation (now part of Microchip Technology) designs high-reliability analog, mixed-signal, and power semiconductors for aerospace, defense, and industrial markets, with emphasis on radiation-hardened and DO-160-qualified components.
The MAPLAD18KP110CAE3 belongs to Microsemi's high-power PLAD TVS family, engineered specifically for multi-stroke lightning protection and high-energy transient suppression in safety-critical avionics and transportation systems.
FAQ
What is the clamping voltage of MAPLAD18KP110CAE3 at its rated peak pulse current?
The MAPLAD18KP110CAE3 has a maximum clamping voltage (VC) of 177 V when subjected to its rated peak pulse current (IPP) of 177 A under 10/1000 μs waveform conditions. This value is measured per Figure 3 in RF01215 Rev B and defines the upper voltage limit imposed on protected circuitry during worst-case surge events. The low VC ensures downstream 200 V-rated components remain within safe operating margins.
Is MAPLAD18KP110CAE3 qualified for RTCA DO-160F lightning testing?
Yes, MAPLAD18KP110CAE3 is explicitly qualified for RTCA DO-160F Section 22 multi-stroke lightning testing, including Waveform 4 (6.4/69 μs) Level 4 and Waveform 5A (40/120 μs) Level 4 - as confirmed in the "Pin injection protection" table on page 1 of RF01215 Rev B. Its 110 V VWM places it within the listed range (MPLAD18KP7.0A to 200CA) for Level 4 compliance.
Does MAPLAD18KP110CAE3 require dry pack or moisture-sensitive handling?
No, MAPLAD18KP110CAE3 has IPC/JEDEC J-STD-020B Moisture Sensitivity Level 1 rating, meaning it does not require dry pack storage or floor-life tracking. The void-free UL94V-0 epoxy body and annealed matte-tin terminations provide inherent moisture resistance, allowing standard SMT handling and reflow without baking or humidity-controlled environments.
What is the thermal resistance from junction to case (RθJC) for MAPLAD18KP110CAE3?
The junction-to-case thermal resistance (RθJC) of MAPLAD18KP110CAE3 is 0.7 °C/W, as specified in the "MAXIMUM RATINGS" table on page 2 of RF01215 Rev B. This ultra-low value results from the metal-base PLAD construction and enables direct thermal coupling to PCB copper or external heatsinks - critical for sustaining repeated 18 kW surges without thermal runaway.
How does the bidirectional configuration of MAPLAD18KP110CAE3 affect PCB layout?
The bidirectional configuration of MAPLAD18KP110CAE3 eliminates polarity concerns in PCB layout: the top pad and metal base serve as symmetrical terminals, allowing placement across any two-node DC or AC line without orientation constraints. However, the metal base must be soldered to a thermally robust copper area (≥1000 mm² recommended) to realize the 0.7 °C/W RθJC - unlike unidirectional variants where cathode assignment matters.
MAPLAD18KP110CAE3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Package/Case:
- Nonstandard SMD
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 110V
- Voltage - Breakdown (Min):
- 122V
- Voltage - Clamping (Max) @ Ipp:
- 177V
- Current - Peak Pulse (10/1000µs):
- 102A
- Power - Peak Pulse:
- 18000W (18kW)
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- Military
- Qualification:
- MIL-PRF-19500
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PLAD
MAPLAD18KP110CAE3 FAQ
1.How can I place an order for MAPLAD18KP110CAE3 through Aetrix?
Please submit a Request for Quotation (RFQ) for MAPLAD18KP110CAE3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MAPLAD18KP110CAE3 reliable?
The price and inventory of MAPLAD18KP110CAE3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MAPLAD18KP110CAE3 is usually 5 days.
3.What payment methods are accepted for MAPLAD18KP110CAE3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MAPLAD18KP110CAE3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MAPLAD18KP110CAE3?
MAPLAD18KP110CAE3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MAPLAD18KP110CAE3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MAPLAD18KP110CAE3?
For technical support, including MAPLAD18KP110CAE3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MAPLAD18KP110CAE3 requirements.
6.How does Aetrix verify that MAPLAD18KP110CAE3 is sourced from the original manufacturer or authorized distributors?
All MAPLAD18KP110CAE3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MAPLAD18KP110CAE3 meets industry standards.
7.What is the process for return or replacement of MAPLAD18KP110CAE3?
All MAPLAD18KP110CAE3 units undergo pre-shipment inspection (PSI). If there is an issue with MAPLAD18KP110CAE3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MAPLAD18KP110CAE3 part is unused and in its original packaging.
Return procedure for MAPLAD18KP110CAE3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MAPLAD18KP110CAE3 Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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onsemi

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Diodes Incorporated

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Diodes Incorporated

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Diodes Incorporated

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ESD5Z5.0T1G
onsemi

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DESD5V0U1BB-7
Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
Nexperia USA Inc.

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Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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