NXP Semiconductors MMA2605KGCWR2
- Part No.:
- MMA2605KGCWR2
- Manufacturer:
- NXP Semiconductors
- Category:
- Accelerometers
- Package:
- 16-QFN Exposed Pad
- Datasheet:
-
MMA2605KGCWR2.pdf
- Description:
- IC SENSOR ACCEL 50G X- AXIS 16QF
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
MMA2605KGCWR2 from NXP Semiconductors is a DSI2.5-compatible, overdamped X-axis satellite accelerometer designed for automotive airbag crash detection. It delivers ±50 g full-scale range, 180 Hz / 400 Hz / 800 Hz selectable low-pass filtering (2- or 4-pole), and operates across -40 °C to +125 °C. Its internal high-side bus switch enables daisy-chain configurations in safety-critical vehicle restraint systems.
For engineers reviewing the MMA2605KGCWR2 datasheet, MMA2605KGCWR2 pinout, MMA2605KGCWR2 application, or MMA2605KGCWR2 equivalent, key selection criteria include AEC-Q100 Grade 1 qualification, DSI2.5 command compliance, programmable LPF configuration, integrated bus switch for multi-sensor networks, and 16-pin QFN package with 6 mm × 6 mm footprint.
Technical Context
The MMA2605KGCWR2 implements a sigma-delta (ΣΔ) ADC with SINC filter compensation and configurable IIR low-pass filtering-supporting three discrete cutoff frequencies (180 Hz/2-pole, 400 Hz/4-pole, 800 Hz/4-pole). Its sensing element features overdamped mechanical response (damping ratio ζ = 2.76 for ±50 g range) and natural frequency of 12.65 kHz, ensuring minimal phase distortion during rapid crash transients.
DSI2.5 interface operation relies on BUSIN-powered signaling with internal rectification via HCAP, regulated digital/analog supplies (VREG/VREGA = 2.5 V ±75 mV), and deterministic timing: 4 MHz internal oscillator, 100–200 kbps data rate, and <5 ms loss-of-signal reset recovery. The device supports OTP-programmable range, LPF, device address, and PCM output enable.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Full-Scale Range | ±50 g - calibrated linear measurement range optimized for front/side airbag deployment thresholds |
| Low-Pass Filter Options | 180 Hz (2-pole), 400 Hz (4-pole), or 800 Hz (4-pole) - selectable via OTP to suppress noise while preserving crash pulse fidelity |
| Operating Temperature | -40 °C to +125 °C - qualified per AEC-Q100 Grade 1 for under-hood and cabin-mounted automotive applications |
| Sensitivity (10-bit) | 10.24 LSB/g - fixed digital gain enabling direct acceleration-to-code conversion without external scaling |
| Internal Oscillator | 4 MHz ±5% - clock source for ADC, DSP, and DSI timing; determines interpolation latency (64–65 cycles) |
| Supply Architecture | BUSIN-powered (6.3–30 V), with HCAP hold capacitor and dual regulated outputs (VREG/VREGA = 2.5 V) |
| Quiescent Current | ≤8.0 mA - enables low-power system-level monitoring during vehicle standby modes |
Pinout & Package
Pb-free 16-pin QFN package, 6 mm × 6 mm × 1.98 mm body, exposed thermal pad connected to VSS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 TEST2 | Test Pin | Must remain unconnected in production; no functional role in normal operation |
| 2 TEST3 | Test Pin | Must be grounded; used internally for factory test mode entry |
| 3 TEST1 | Test Pin | Must be grounded; part of factory test infrastructure, not user-accessible |
| 4 BUSRTN | Common Return | Shared ground reference for DSI bus power and signaling; critical for noise immunity in daisy-chain topologies |
| 5 PCM | PCM Output | 4 MHz pulse-code modulated signal proportional to acceleration; enabled/disabled via OTP bit DEVCFG2[5] |
| 6 BUSOUT | DSI Bus Output | Internally switched connection to BUSIN; closes after Initialization command to enable slave chaining |
| 7 BUSIN | DSI Power/Comm | Primary DSI node: supplies power (6.3–30 V) and receives commands; requires external decoupling capacitor to BUSRTN |
| 8 HCAP | Hold Capacitor | Rectifies BUSIN voltage; stores energy for uninterrupted operation during master signaling gaps |
| 9 CREG | Digital Supply | Input to internal digital regulator (VREG); requires 500–1500 nF ceramic capacitor to VSS |
| 10 TEST4 | Test Pin | Must be grounded; reserved for wafer-level characterization |
| 11 CREGA | Analog Supply | Input to internal analog regulator (VREGA); requires 500–1500 nF ceramic capacitor to VSSA |
| 12 VSSA | Analog Ground | Dedicated return for analog circuitry; must be isolated from digital ground except at single-point VSS tie |
| 13 TEST5 | Test/Programming | Ground in application; provides SPI programming voltage during test mode |
| 14 TEST6 | Test Pin | Must be grounded; no user-accessible function |
| 15 TEST7 | Test Pin | Must be grounded; factory test only |
| 16 VSS | Digital Ground | Return path for digital logic and regulators; connects to exposed thermal pad |
Key Features
| Feature | Design Value |
|---|---|
| DSI2.5 Compliance | Full support of mandatory commands (Initialization, Request ID, Clear, Read/Write NVM) ensures interoperability in multi-node safety buses |
| Integrated High-Side Bus Switch | Enables seamless daisy-chaining of up to 16 accelerometers on one DSI bus without external switches or level shifters |
| Overdamped Sensing Element | Damping ratio ζ = 2.76 eliminates resonance artifacts during high-slew crash events, delivering clean transient response |
| Self-Test Capability | Electrostatic actuation provides repeatable deflection (123 LSB @ ±50 g) for in-system functional verification pre-deployment |
| AEC-Q100 Grade 1 Qualification | Validated for -40 °C to +125 °C operation with 2000 g powered/unpowered shock tolerance and 1.2 m drop survivability |
Applications
| Front Airbag Crash Detection | Side-Impact Airbag Activation |
|---|---|
Use Scenario: Detects rapid deceleration (>20 g) during frontal collisions to trigger driver/passenger airbag inflation within 20 ms. IC Role / Device Role / Timing Role: Primary X-axis inertial sensor providing real-time acceleration data to airbag control unit (ACU) via DSI2.5 bus. Use Value: ±50 g range and 180 Hz LPF optimize signal-to-noise ratio for crash pulse discrimination while rejecting road noise and vibration. | Use Scenario: Mounted in B-pillar or door to sense lateral acceleration during side collisions, initiating curtain and seat-mounted airbags. IC Role / Device Role / Timing Role: Dedicated X-axis satellite accelerometer feeding time-critical data to ACU over daisy-chained DSI bus. Use Value: Internal bus switch allows multiple sensors (front, side, rollover) to share one DSI master, reducing wiring harness complexity and ECU pin count. |
| Rollover Detection Support | Occupant Position Sensing Interface |
Use Scenario: Monitors longitudinal and lateral acceleration components to compute vehicle roll angle and angular rate for rollover prediction. IC Role / Device Role / Timing Role: Secondary X-axis sensor augmenting primary IMU; communicates via same DSI network with synchronized timestamps. Use Value: 400 Hz LPF option preserves higher-frequency dynamics needed for accurate roll-rate estimation without aliasing. | Use Scenario: Integrated into seat structure to detect occupant presence, position, and weight for adaptive airbag deployment logic. IC Role / Device Role / Timing Role: Low-power satellite node providing static/dynamic acceleration data to occupant classification ECU. Use Value: ≤8 mA quiescent current and BUSIN-powered architecture eliminate need for separate low-voltage supply rails in seat electronics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inertial sensor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MMA2602KGCWR2 | ±25 g full-scale range; identical pinout, DSI interface, and package; lower sensitivity (20.48 LSB/g) | Optimized for lower-threshold crash detection (e.g., pedestrian impact, low-speed collisions) | Select when system requires higher resolution at reduced range and lower g-cell clipping limits (456 g vs. 500 g) |
| MMA2612KGCWR2 | ±125 g full-scale range; same DSI2.5 compliance and QFN-16 package; sensitivity 4.096 LSB/g | Suitable for high-g environments (e.g., rollover, rear-impact, heavy-truck airbag systems) | Choose for applications demanding extended overload margin and compatibility with higher-magnitude crash pulses |
Compared with MMA2602KGCWR2 and MMA2612KGCWR2, the MMA2605KGCWR2 strikes a balance between resolution and dynamic range for mainstream automotive front/side airbag systems, offering optimal SNR at 50 g while maintaining AEC-Q100 Grade 1 reliability and DSI2.5 interoperability.
Availability
MMA2605KGCWR2 is available at Aetrix Electronics and suitable for automotive safety systems, airbag control units, and crash event recorders requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant traceability.
Supply support for MMA2605KGCWR2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The MMA26xx family is part of NXP's SafeAssure portfolio, engineered specifically for ASIL-B compliant automotive safety systems-delivering robust, fault-tolerant inertial sensing with DSI2.5 interface for airbag and restraint control.
FAQ
What is the full-scale range and sensitivity of the MMA2605KGCWR2?
The MMA2605KGCWR2 has a nominal full-scale range of ±50 g and a sensitivity of 10.24 LSB/g in 10-bit output mode. This value is factory-trimmed and stored in OTP, ensuring consistent scaling across temperature (-40 °C to +125 °C) without external calibration. The MMA2605KGCWR2 achieves this using an overdamped MEMS g-cell and sigma-delta ADC with SINC filter compensation.
How does the DSI2.5 interface of the MMA2605KGCWR2 support daisy-chain configurations?
The MMA2605KGCWR2 integrates an internal high-side bus switch that connects BUSIN to BUSOUT upon receiving a DSI Initialization command. This enables up to 16 devices to be wired in series on a single DSI bus, with each device forwarding commands downstream. The MMA2605KGCWR2's BUSRTN serves as common return, and its 100–200 kbps data rate ensures deterministic timing for safety-critical airbag decisions.
What low-pass filter options are available on the MMA2605KGCWR2 and how are they configured?
The MMA2605KGCWR2 offers three programmable low-pass filter options: 180 Hz (2-pole), 400 Hz (4-pole), and 800 Hz (4-pole), selected via OTP bits LPF[1:0] in the TYPE register. These filters are implemented digitally in the DSP block and affect both noise rejection and phase delay-180 Hz provides maximum noise suppression for crash pulse isolation, while 800 Hz preserves higher-frequency content for rollover detection. Configuration occurs during programming and is non-volatile.
Is the MMA2605KGCWR2 qualified for automotive use and what standards does it meet?
Yes, the MMA2605KGCWR2 is qualified to AEC-Q100 Revision G, Grade 1 (-40 °C to +125 °C), with full validation for powered/unpowered shock (±2000 g), drop survivability (1.2 m), and ESD (HBM ±2000 V). It is part of NXP's SafeAssure solution suite, targeting ASIL-B compliance in airbag control units. The MMA2605KGCWR2 also meets ISO 26262 functional safety requirements for hardware development processes.
What external components are required for proper operation of the MMA2605KGCWR2?
The MMA2605KGCWR2 requires five external capacitors: C1/C2 (100–1500 pF, X7R, 50 V) on BUSIN/BUSOUT for ESD and decoupling; C3 (1–100 μF, X7R, 50 V) as reservoir capacitor on HCAP; and C4/C5 (1 μF, X7R, 10 V) on CREG/CREGA for regulator stability. No resistors or active components are needed-the MMA2605KGCWR2 integrates all regulation, filtering, and interface logic on-die.
MMA2605KGCWR2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- MMA
- Package/Case:
- 16-QFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Digital
- Axis:
- X
- Acceleration Range:
- ±50g
- Sensitivity (LSB/g):
- -
- Sensitivity (mV/g):
- -
- Bandwidth:
- -
- Output Type:
- -
- Voltage - Supply:
- 6.3V ~ 30V
- Features:
- -
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (6x6)
MMA2605KGCWR2 FAQ
1.How can I place an order for MMA2605KGCWR2 through Aetrix?
Please submit a Request for Quotation (RFQ) for MMA2605KGCWR2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MMA2605KGCWR2 reliable?
The price and inventory of MMA2605KGCWR2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MMA2605KGCWR2 is usually 5 days.
3.What payment methods are accepted for MMA2605KGCWR2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MMA2605KGCWR2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MMA2605KGCWR2?
MMA2605KGCWR2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MMA2605KGCWR2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MMA2605KGCWR2?
For technical support, including MMA2605KGCWR2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MMA2605KGCWR2 requirements.
6.How does Aetrix verify that MMA2605KGCWR2 is sourced from the original manufacturer or authorized distributors?
All MMA2605KGCWR2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MMA2605KGCWR2 meets industry standards.
7.What is the process for return or replacement of MMA2605KGCWR2?
All MMA2605KGCWR2 units undergo pre-shipment inspection (PSI). If there is an issue with MMA2605KGCWR2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MMA2605KGCWR2 part is unused and in its original packaging.
Return procedure for MMA2605KGCWR2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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