My Inquiry
My Account
NXP Semiconductors MMA8125EG
- Part No.:
- MMA8125EG
- Manufacturer:
- NXP Semiconductors
- Category:
- Accelerometers
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
MMA8125EG.pdf
- Description:
- ACCEL 250G DSI/SPI 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,244
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
MMA8125EG from Freescale Semiconductor is a Z-axis single-axis digital accelerometer with 250g full-scale range, DSI 2.0 serial interface, and automotive AEC-Q100 qualification. It integrates capacitance-to-voltage conversion, 2-stage switched-capacitor amplification, Bessel filtering (180 Hz 2-pole or 400 Hz 4-pole), and on-chip voltage regulation for crash detection in airbag control units.
For engineers reviewing the MMA8125EG datasheet, MMA8125EG pinout, MMA8125EG application, or MMA8125EG equivalent, key selection criteria include Z-axis orientation, DSI bus compatibility, 10-bit digital output resolution, 6.3–30 V supply operation, and ground-loss detection capability in safety-critical automotive modules.
Technical Context
The MMA8125EG implements a variable-capacitance Z-axis sensing element interfaced to a dedicated ASIC that performs C-to-V conversion, offset/gain trimming, and Bessel-filtered signal conditioning. Its internal 4 MHz temperature-compensated oscillator provides timing for the DSI 2.0 protocol stack and ADC sampling.
Signal path includes a low-pass switched-capacitor filter (configurable as 180 Hz 2-pole or 400 Hz 4-pole), 10-bit successive-approximation ADC, and serial output stage compliant with DSI 2.0 physical and data-link layers - supporting both short-word and long-word command/response formats over a daisy-chainable bus.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Axis Orientation | Z-axis only; mechanical sensitivity aligned perpendicular to package top surface |
| Full-Scale Range | ±250 g; calibrated and factory-trimmed for high-shock event detection |
| Digital Output Resolution | 10-bit; provides 1024 discrete acceleration levels across full scale |
| Supply Voltage Range | 6.3 V to 30 V; supports direct connection to automotive battery/bus without external regulator |
| Filter Options | 180 Hz 2-pole or 400 Hz 4-pole Bessel response; preserves transient fidelity while rejecting high-frequency noise |
| Interface Standard | DSI 2.0 compliant; enables daisy-chained topology with reverse initialization fault tolerance |
| Operating Temperature | −40 °C to +125 °C; qualified per AEC-Q100 Grade 1 for under-hood automotive use |
Pinout & Package
Package: 16-pin SOIC (Case 475-01), RoHS-compliant, surface-mountable with standard reflow profile.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| N/C | No internal connection | Unbonded pad; must remain floating or grounded per layout best practice |
| VSS | Power return | Internally tied to BUSRTN; all VSS pins must connect to common bus return on PCB |
| CREG | Regulator stability capacitor node | Connects to external 1 µF capacitor for internal voltage regulator stability; dual pins provided for redundancy |
| BUSRTN | Bus power and signal return | Common reference for BUSIN/BUSOUT signaling and power rectification; ties to chassis ground in single-ended systems |
| VPP/TEST | OTP programming/test voltage | Factory test interface; must be connected to ground in end application to prevent unintended access |
| HCAP | Hold capacitor node | Stores energy for DSI bus transitions; requires short, low-inductance trace to external 1 µF capacitor |
| CFIL | Filtered analog output monitor | Provides buffered access to Bessel-filtered sensor signal; used for diagnostics or external ADC sampling |
| DOUT | Serial data output | DSI bus data output during master-read operations; open-drain with internal pull-up |
| VGND/DIN | Ground-loss detection / test-mode input | Enables open-ground fault detection when GLDE bit is set; functions as SPI DIN in test mode |
| CLK | Test clock input | Used only during factory OTP programming; leave unconnected in application; avoid shorting to adjacent VGND/DIN |
| BUSIN | Primary DSI bus input | Receives commands from master; supports reverse initialization if BUSOUT is used as alternate input |
| BUSOUT | DSI bus output / reverse-input | Drives downstream devices in daisy chain; configurable as input for fault-tolerant reverse initialization |
| VSS (repeated) | Power return | Second VSS pin; internally connected to BUSRTN; must tie to same net as other VSS pins |
| CREG (repeated) | Regulator stability capacitor node | Redundant CREG pin; recommended to connect both CREG pins to same external capacitor |
| VSS (third) | Power return | Third VSS pin; ensures low-impedance return path for internal regulator and logic |
Key Features
| Feature | Design Value |
|---|---|
| Z-axis transducer with overdamped response | Minimizes resonance artifacts during high-g shock events like crash impact, improving airbag deployment timing accuracy |
| 80-bit customer-accessible OTP memory | Enables field-programmable device configuration, serial number storage, and custom attribute coding without external EEPROM |
| Integrated ground-loss detection (GLDE) | Monitors resistance between VGND/DIN and chassis ground; asserts GF flag and returns zero data if open fault exceeds 4.096 ms |
| Self-test with factory-trimmed voltage | Electrostatic deflection stimulus verifies mechanical integrity and signal chain functionality at power-on or on-demand |
| Undervoltage monitoring on HCAP | Halts data transmission and sets U flag if HCAP drops below operating threshold; triggers POR if condition persists >1 ms |
Applications
| Crash Detection (Airbag Systems) | Impact Monitoring (Industrial Machinery) |
|---|---|
Use Scenario: Real-time detection of rapid deceleration exceeding 200 g during frontal collision to trigger airbag inflation within 20 ms. IC Role / Device Role / Timing Role: Primary Z-axis inertial sensor providing time-critical acceleration data to airbag control unit via DSI 2.0 bus. Use Value: Overdamped Z-axis response eliminates ringing artifacts, enabling deterministic threshold crossing and reducing false deployment risk. | Use Scenario: Continuous monitoring of vibration and impact events on hydraulic presses or forging equipment to detect tool failure or misalignment. IC Role / Device Role / Timing Role: Standalone shock event logger capturing peak g-levels and timestamps using internal self-test and OTP-stored calibration data. Use Value: 250 g range and −40 °C to +125 °C operation allow direct mounting near high-heat machinery without derating or external protection. |
| Shock Detection (Transportation Logging) | Vibration Analysis (Railway Bogies) |
Use Scenario: Recording shock events during cargo transport to assess handling severity and validate packaging integrity. IC Role / Device Role / Timing Role: Battery-powered DSI satellite node reporting peak acceleration values and timestamps to central gateway via daisy-chained bus. Use Value: Wide 6.3–30 V supply range enables direct connection to vehicle auxiliary power; low external component count reduces system BOM cost. | Use Scenario: Mounting on railway bogie frames to capture vertical acceleration profiles during track irregularity events (e.g., rail joint impacts). IC Role / Device Role / Timing Role: High-reliability Z-axis sensor feeding filtered analog output (CFIL) to external DAQ system for spectral analysis. Use Value: Bessel-filtered 180 Hz 2-pole output preserves transient shape for accurate FFT-based defect classification without phase distortion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar single-axis accelerometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MMA8115EG | Same Z-axis SOIC package and DSI 2.0 interface, but ±150 g full-scale range and no 250 g calibration | Suitable for lower-shock environments (e.g., rollover detection); lacks margin for extreme crash pulse capture | Select MMA8115EG only if system-level shock testing confirms <150 g peak events and cost optimization is prioritized |
| ADXL372BCCZ | ±200 g range, I²C/SPI interface, 2.5 V supply, 22-bit output; no DSI or automotive qualification | Requires level-shifting and external regulator for 12 V automotive bus; not AEC-Q100 qualified | Consider ADXL372BCCZ only for non-safety-critical industrial logging where higher resolution outweighs bus compatibility and qualification needs |
Compared with MMA8115EG and ADXL372BCCZ, the MMA8125EG uniquely delivers 250 g Z-axis measurement with native DSI 2.0 daisy-chain support, AEC-Q100 Grade 1 qualification, and integrated ground-loss detection - making it the only option qualified for production airbag satellite modules requiring fail-safe bus communication and open-ground fault reporting.
Availability
MMA8125EG is available at Aetrix Electronics and suitable for crash detection (airbag), impact monitoring (industrial machinery), and shock detection (transportation logging) requiring stable component supply across automotive Tier-1 and industrial OEM programs.
Supply support for MMA8125EG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Freescale Semiconductor (now part of NXP Semiconductors) is a global leader in automotive and industrial microcontrollers, sensors, and analog ICs, with deep expertise in safety-critical embedded systems.
The MMA81XXEG series was designed specifically for satellite accelerometer roles in DSI 2.0 automotive networks - emphasizing robustness, bus fault tolerance, and integration of diagnostics like ground-loss detection and self-test.
FAQ
What is the full-scale range and axis orientation of the MMA8125EG?
The MMA8125EG is a Z-axis single-axis accelerometer with a calibrated full-scale range of ±250 g. Its mechanical sensitivity is oriented perpendicular to the top surface of the 16-pin SOIC package. This orientation is factory-trimmed and verified, and the AXIS bit in the Type Byte (OTP address $04, bit 5) is set to '0' to confirm Z-axis configuration. The MMA8125EG does not support X-axis or multi-axis operation.
Does the MMA8125EG support daisy-chained DSI bus configurations?
Yes, the MMA8125EG fully supports daisy-chained DSI 2.0 bus topologies via its BUSIN and BUSOUT pins. In normal operation, BUSIN receives commands from the master and BUSOUT drives the next device. The device also supports reverse initialization for fault tolerance: if BUSIN communication fails, the master can use BUSOUT as an input while repurposing BUSIN to access other nodes. The bus switch is controlled by D6 in Initialization/Reverse Initialization commands.
How does ground-loss detection work on the MMA8125EG?
Ground-loss detection on the MMA8125EG is enabled by setting the GLDE bit (DEVCFG2[5]) to '1'. The VGND/DIN pin then sources a constant current into the chassis ground path. If resistance exceeds the threshold, voltage rises and triggers a 14-bit counter. Overflow after 4.096 ms asserts the Ground Fault (GF) flag and causes Read Acceleration Data commands to return zero. This feature is disabled in differential DSI mode, where VGND/DIN must connect directly to BUSRTN.
What filter options are available on the MMA8125EG and how are they selected?
The MMA8125EG offers two Bessel filter configurations: 180 Hz 2-pole and 400 Hz 4-pole. Selection is determined by the ORDER bit (TYPE register, $04 bit 7): '0' selects 400 Hz 4-pole, '1' selects 180 Hz 2-pole. This bit is factory-programmed and read-only during operation. The filtered analog signal is accessible at the CFIL pin, and the same filter applies to the 10-bit ADC output used for DSI data transmission.
Is the MMA8125EG qualified for automotive applications?
Yes, the MMA8125EG is qualified to AEC-Q100 Grade 1 standards (−40 °C to +125 °C) and is RoHS compliant. It includes automotive-specific features such as undervoltage lockout with POR, ground-loss detection, self-test with factory-trimmed stimulus, and DSI 2.0 fault-tolerant bus architecture - all validated for use in safety-critical satellite accelerometer roles including airbag control units and electronic stability control subsystems.
MMA8125EG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Digital
- Axis:
- Z
- Acceleration Range:
- ±250g
- Sensitivity (LSB/g):
- 1
- Sensitivity (mV/g):
- -
- Bandwidth:
- -
- Output Type:
- DSI, SPI
- Voltage - Supply:
- 6.3V ~ 30V
- Features:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
MMA8125EG FAQ
1.How can I place an order for MMA8125EG through Aetrix?
Please submit a Request for Quotation (RFQ) for MMA8125EG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for MMA8125EG reliable?
The price and inventory of MMA8125EG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for MMA8125EG is usually 5 days.
3.What payment methods are accepted for MMA8125EG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for MMA8125EG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for MMA8125EG?
MMA8125EG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your MMA8125EG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for MMA8125EG?
For technical support, including MMA8125EG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your MMA8125EG requirements.
6.How does Aetrix verify that MMA8125EG is sourced from the original manufacturer or authorized distributors?
All MMA8125EG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that MMA8125EG meets industry standards.
7.What is the process for return or replacement of MMA8125EG?
All MMA8125EG units undergo pre-shipment inspection (PSI). If there is an issue with MMA8125EG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The MMA8125EG part is unused and in its original packaging.
Return procedure for MMA8125EG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
MMA8125EG Tags
-
MXC4005XC
Memsic Inc.
-
MC3419
Memsic Inc.
-
MC3479
Memsic Inc.
-
MXC6655XA
Memsic Inc.
-
MC3630
Memsic Inc.
.jpg)
-
LIS2HH12TR
STMicroelectronics
-
KX122-1037
Kionix Inc.
-
LIS2DE12TR
STMicroelectronics
-
LIS2DH12TR
STMicroelectronics
-
MC3635
Memsic Inc.
-
LIS2DS12TR
STMicroelectronics
-
LIS3DHTR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
