NXP Semiconductors NT2H1001G0DUDV
- Part No.:
- NT2H1001G0DUDV
- Manufacturer:
- NXP Semiconductors
- Category:
- RFID, RF Access, Monitoring ICs
- Package:
- Die
- Datasheet:
-
NT2H1001G0DUDV.pdf
- Description:
- IC RFID TRANSP 13.56MHZ DIE
- Quantity:
- Payment:

- Shipping:

Inventory:1,993
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NT2H1001G0DUDV from NXP Semiconductors is an NFC Forum Type 2 Tag compliant contactless IC designed for mass-market smart tagging applications. It operates at 13.56 MHz, delivers 106 kbit/s data transfer, provides 48 bytes of user EEPROM memory, and features a pre-programmed 7-byte UID with ECC-based originality signature for authentication. It is deployed in NFC shelf labels, product authentication tags, and mobile companion tags.
For engineers reviewing the NT2H1001G0DUDV datasheet, NT2H1001G0DUDV pinout, NT2H1001G0DUDV application, or NT2H1001G0DUDV equivalent, key selection considerations include its 50 pF input capacitance variant, 75 µm die thickness for ultrathin inlay integration, field-programmable page locking, anti-tearing support for capability container, and ISO/IEC 14443 Type A compliance.
Technical Context
The NT2H1001G0DUDV implements a fully integrated RF interface per ISO/IEC 14443 Type A, including rectifier, clock regenerator, POR, and voltage regulator - requiring no external components beyond an antenna coil. Its Digital Control Unit executes anticollision (cascade level 1 and 2), command interpretation (READ, WRITE, GET_VERSION, READ_SIG), and EEPROM interface control.
Memory organization comprises 64 bytes of EEPROM in 16 pages (4 bytes/page): 10 bytes reserved for UID and configuration, 4 bytes for capability container (CC), 16 bits for static lock bytes, and 48 bytes user memory (pages 04h–0Fh). All memory operations occur in the ACTIVE state, entered via SELECT or direct READ from address 0.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Frequency | 13.56 MHz - Enables interoperability with all NFC Forum–compliant readers and smartphones. |
| Data Transfer Rate | 106 kbit/s - Standard Type A low-speed mode supporting reliable short-range communication. |
| User Memory Size | 48 bytes (12 pages) - Sufficient for NDEF messages like URLs, text records, or small authentication payloads. |
| Input Capacitance | 50 pF - Matches antenna tuning requirements for optimized RF performance in thicker inlay substrates. |
| EEPROM Endurance | 100,000 write cycles - Supports repeated reprogramming in dynamic tag applications like event tickets or reusable vouchers. |
| Data Retention | 10 years at 22 °C - Ensures long-term reliability in consumer-facing printed media and retail labels. |
| UID Length | 7-byte serial number (cascade level 2) - Provides globally unique identification required for secure authentication and inventory tracking. |
Pinout & Package
NT2H1001G0DUDV is supplied as a bare die in FFC Bump packaging with 75 µm thickness on film frame carrier. It features two antenna terminals only - no conventional package pins - and requires direct wire bonding or flip-chip attachment to an external coil.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LA | Antenna connection LA | Primary RF input terminal; connects to one end of the loop antenna coil for energy harvesting and bidirectional data coupling. |
| LB | Antenna connection LB | Secondary RF input terminal; completes the resonant LC circuit with LA and external antenna inductance. |
Key Features
| Feature | Design Value |
|---|---|
| NFC Forum Type 2 Tag Compliance | Fully conforms to NFC Forum Technical Specification and ISO/IEC 14443-3A, enabling plug-and-play interoperability with Android/iOS NFC hosts. |
| Field-Programmable Page Locking | Per-page read-only locking (pages 03h–0Fh) via static lock bytes - allows selective memory protection without full write-disable. |
| ECC-Based Originality Signature | 32-byte secp128r1 ECDSA signature stored in hidden memory, verifiable offline using NXP's public key - enables counterfeit detection in brand protection use cases. |
| Anti-Tearing Protection | Hardware-enforced atomic update for capability container and lock bits - prevents corruption during power loss mid-write in industrial environments. |
| Ultrathin Die Profile | 75 µm thickness enables embedding into paper, PET, or thin laminates - critical for magazine-integrated tags and gaming card applications. |
Applications
| Smart Retail Shelf Labels | Product Authentication Tags |
|---|---|
|
Use Scenario: NFC-enabled price labels on supermarket shelves updated wirelessly via handheld reader. IC Role / Device Role / Timing Role: Passive NFC tag IC storing dynamic pricing, stock status, and promotional content in NDEF format. Use Value: Eliminates manual label replacement; 48-byte memory supports multi-language price + expiry date + QR fallback. |
Use Scenario: Tamper-evident NFC tag embedded in luxury handbag lining or pharmaceutical packaging. IC Role / Device Role / Timing Role: Secure identity anchor providing cryptographically verifiable origin proof via READ_SIG command. Use Value: Pre-programmed ECC signature prevents cloning; 7-byte UID + locked signature ensures traceability across supply chain. |
| Print Media Companion Tags | Gaming Card Interaction |
|
Use Scenario: NFC spot on magazine cover launching AR experience or video demo when tapped by smartphone. IC Role / Device Role / Timing Role: Low-power passive tag delivering URL or MIME-type payload to trigger native app behavior. Use Value: 106 kbit/s transfer ensures sub-200 ms response; 75 µm die allows seamless lamination into 170 gsm coated paper. |
Use Scenario: Collectible trading card with NFC-triggered game unlock or character profile loading. IC Role / Device Role / Timing Role: Identity and data carrier storing player ID, unlock flags, and session tokens in protected user memory. Use Value: Field-programmable locking secures sensitive game assets; 100,000 write cycles support lifetime usage across multiple titles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NFC tag IC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NT2L1001G0DUDV | 17 pF input capacitance, 120 µm die thickness | Better suited for rigid inlays or thicker laminates where lower capacitance eases antenna tuning | Select when mechanical robustness or compatibility with legacy 17 pF antenna designs is required |
| NT3H1101W0FTH | 1 KB user memory, I²C + NFC dual-interface, 3.3 V supply, 1.2 mm QFN package | Active hybrid IC for battery-powered accessories or developer kits requiring host microcontroller interfacing | Choose only if system-level design requires wired configuration or >100× more memory - not a drop-in replacement |
Compared with NT2L1001G0DUDV, the NT2H1001G0DUDV offers higher RF coupling margin in flexible-thickness inlays due to its 50 pF capacitance, while NT3H1101W0FTH introduces active functionality incompatible with pure passive tag deployment - making NT2H1001G0DUDV optimal for cost-sensitive, high-volume printed NFC applications.
Availability
NT2H1001G0DUDV is available at Aetrix Electronics and suitable for smart retail shelf labels, product authentication systems, and print media companion tags requiring stable component supply across global manufacturing programs.
Supply support for NT2H1001G0DUDV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer markets, with core expertise in RFID, NFC, and secure element technologies.
The NTAG family, including NT2H1001G0DUDV, was engineered specifically for high-volume, cost-optimized NFC tagging in retail, publishing, and gaming - prioritizing RF robustness, memory security, and ultrathin form factor manufacturability.
FAQ
What is the primary function of the NT2H1001G0DUDV in an NFC system?
The NT2H1001G0DUDV serves as a passive NFC Forum Type 2 Tag IC that receives power and exchanges data wirelessly via magnetic induction at 13.56 MHz. It stores up to 48 bytes of user data, authenticates origin via ECC signature, and supports field-programmable memory locking - enabling secure, maintenance-free tagging in retail, authentication, and interactive media applications. The NT2H1001G0DUDV requires no battery or external power source.
How does the 50 pF input capacitance of NT2H1001G0DUDV affect antenna design?
The 50 pF input capacitance of NT2H1001G0DUDV sets the resonant tuning point when paired with an external antenna coil, allowing greater flexibility in antenna geometry and substrate choice - especially for thicker or lossier materials like corrugated cardboard or laminated plastic. This value reduces sensitivity to parasitic capacitance variations compared to the 17 pF NT2L1001G0DUDV variant, improving yield in high-volume inlay production. NT2H1001G0DUDV must be matched to an antenna with corresponding inductance to achieve 13.56 MHz resonance.
Can the originality signature of NT2H1001G0DUDV be customized, and how is it verified?
Yes, the NT2H1001G0DUDV ships with a factory-programmed NXP ECC-based originality signature (32 bytes, secp128r1 curve), which can be unlocked using LOCK_SIG, replaced with a custom signature via WRITE_SIG, and permanently re-locked. Verification occurs offline in the NFC host device using NXP's published public key and standard ECDSA validation - no cloud dependency. The READ_SIG command retrieves the signature, and the process is supported by OpenSSL and other open crypto libraries per NXP Application Note AN11756.
What memory protection mechanisms does NT2H1001G0DUDV provide?
NT2H1001G0DUDV implements three hardware-enforced memory protections: (1) per-page read-only locking via static lock bytes (pages 03h–0Fh), (2) anti-tearing for capability container and lock bit writes to prevent corruption during power loss, and (3) factory-programmed UID and ECC signature stored in write-protected memory regions. These features allow selective data hardening - for example, locking product ID pages while leaving coupon redemption fields writable - without compromising overall memory usability.
Is NT2H1001G0DUDV compatible with standard NFC smartphones and readers?
Yes, NT2H1001G0DUDV is fully compliant with NFC Forum Type 2 Tag specification and ISO/IEC 14443 Type A, ensuring interoperability with all Android devices supporting Host Card Emulation (HCE), iOS devices with NFC reading capability (iPhone 7+), and commercial NFC readers like ACS ACR122U or Feitian SCL3711. It responds to standard commands (READ, WRITE, GET_VERSION, READ_SIG) and uses standard framing, CRC, and anticollision protocols - no proprietary drivers or firmware required for basic operation.
NT2H1001G0DUDV Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- Die
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- RFID Transponder
- Frequency:
- 13.56MHz
- Standards:
- ISO 14443
- Interface:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -25°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- Die
NT2H1001G0DUDV FAQ
1.How can I place an order for NT2H1001G0DUDV through Aetrix?
Please submit a Request for Quotation (RFQ) for NT2H1001G0DUDV on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NT2H1001G0DUDV reliable?
The price and inventory of NT2H1001G0DUDV are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NT2H1001G0DUDV is usually 5 days.
3.What payment methods are accepted for NT2H1001G0DUDV?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NT2H1001G0DUDV transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NT2H1001G0DUDV?
NT2H1001G0DUDV orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NT2H1001G0DUDV order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NT2H1001G0DUDV?
For technical support, including NT2H1001G0DUDV datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NT2H1001G0DUDV requirements.
6.How does Aetrix verify that NT2H1001G0DUDV is sourced from the original manufacturer or authorized distributors?
All NT2H1001G0DUDV products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NT2H1001G0DUDV meets industry standards.
7.What is the process for return or replacement of NT2H1001G0DUDV?
All NT2H1001G0DUDV units undergo pre-shipment inspection (PSI). If there is an issue with NT2H1001G0DUDV, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NT2H1001G0DUDV part is unused and in its original packaging.
Return procedure for NT2H1001G0DUDV:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NT2H1001G0DUDV Tags

-
SL2S2602FTBX
NXP Semiconductors

-
ST25DV04K-IER6S3
STMicroelectronics

-
ST25DV04K-IER6C3
STMicroelectronics

-
LXMSJZNCMD-217
Murata Electronics

-
NT3H2111W0FTTJ
NXP Semiconductors

-
NT3H2111W0FHKH
NXP Semiconductors

-
M24LR04E-RMC6T/2
STMicroelectronics

-
ST25DV04KC-JF6D3
STMicroelectronics

-
ST25DV64KC-IE6S3
STMicroelectronics
-
ST25DV64K-IER6T3
STMicroelectronics

-
NT3H2211W0FTTJ
NXP Semiconductors

-
NT3H2211W0FHKH
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
