onsemi NUP2201MR6T1G
- Part No.:
- NUP2201MR6T1G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SOT-23-6 Thin, TSOT-23-6
- Datasheet:
-
NUP2201MR6T1G.pdf
- Description:
- TVS DIODE 5VWM 20VC 6TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:9,060
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Product details
Overview
NUP2201MR6T1G from onsemi is a low-capacitance, unidirectional ESD protection diode array in TSOP-6 package, designed to clamp transients on high-speed data lines to ≤12.5 V at 5 A, with 5.0 V working reverse voltage and 3.0–5.0 pF junction capacitance between I/O and GND. It protects USB 1.1/2.0 data and power lines per IEC 61000-4-2 Level 4 (±20 kV air/±20 kV contact).
For engineers reviewing the NUP2201MR6T1G datasheet, pinout, applications, or equivalent options, key selection criteria include clamping voltage under 8×20 µs surge, low I/O-to-GND capacitance for signal integrity, and AEC-Q101 qualification for automotive-grade reliability.
Technical Context
The NUP2201MR6T1G integrates two steering diodes and one bidirectional surge protection diode in a single TSOP-6 package. Its internal configuration supports three reference modes: VCC-referenced (pin 5 tied to supply), resistor-isolated VCC bias (10 kΩ), or floating reference using the internal surge diode's breakdown voltage.
Clamping behavior is defined by forward conduction of steering diodes (VF ≈ 0.7 V) combined with the surge diode's VRWM = 5.0 V and VC = 12.5 V @ IPP = 5 A. Junction capacitance is specified separately for I/O-to-GND (3.0–5.0 pF) and I/O-to-I/O (1.5–3.0 pF), enabling optimization for differential or single-ended line protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Working Reverse Voltage | 5.0 V - Matches standard 5 V USB and DVI power rails without leakage-induced false triggering |
| Clamping Voltage @ 5 A | 12.5 V - Limits transient overvoltage to safe levels for 3.3 V/5 V logic interfaces during IEC 61000-4-2 events |
| Junction Capacitance (I/O–GND) | 3.0–5.0 pF - Enables use on USB 2.0 (480 Mbps) and DVI data lines without signal distortion |
| ESD Rating (IEC 61000-4-2) | ±20 kV contact - Meets industrial and automotive system-level ESD immunity requirements |
| Peak Pulse Current | 25 A (8×20 µs) - Sustains high-energy lightning-induced surges without degradation |
| Operating Temperature | −40 °C to +125 °C - Supports under-hood automotive and industrial ambient conditions |
| AEC-Q101 Qualified | Yes - Validated for automotive electronics per stress test requirements including HTGB, TCT, and H3TRB |
Pinout & Package
TSOP-6 package (Case 318G), dimensions 3.00 × 1.50 × 0.90 mm, 0.95 mm pitch, Pb-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 (I/O) | Data line input/output terminal | Protected signal path; connects to USB D+ or D−, DVI TMDS channel, or display interface line |
| Pin 2 (VN) | Negative reference / ground return | Must connect directly to low-inductance ground plane to minimize clamping voltage overshoot during fast ESD transients |
| Pin 3 (N/C) | No connection | Internally unconnected; PCB pad may be omitted or left floating-no routing required |
| Pin 4 (N/C) | No connection | Internally unconnected; electrically isolated-no thermal or electrical function |
| Pin 5 (VP) | Positive reference / VCC bias node | Optional connection to 5 V rail to reduce diode capacitance; enables bias-dependent performance tuning |
| Pin 6 (I/O) | Data line input/output terminal | Second protected signal path; used for differential pair protection or dual independent lines |
Key Features
| Feature | Design Value |
|---|---|
| Low I/O-to-GND capacitance | 3.0–5.0 pF ensures minimal signal rise-time degradation on USB 2.0 and DVI links |
| Integrated dual-steering + surge diode topology | Eliminates need for discrete diode networks, reducing board area and parasitic inductance |
| VCC-biasable reference (pin 5) | Enables capacitance reduction and tighter clamping control via external 5 V supply or 10 kΩ isolation resistor |
| AEC-Q101 qualification | Validates reliability for automotive infotainment, ADAS camera links, and body control modules |
| UL 94 V-0 flammability rating | Meets safety standards for enclosure-integrated protection in consumer and industrial end equipment |
Applications
| USB 2.0 Port Protection | DVI Interface Protection |
|---|---|
|
Use Scenario: Protecting upstream/downstream USB ports against ESD during cable insertion or handling. IC Role / Device Role / Timing Role: ESD clamping device placed between connector and USB controller PHY, operating in real-time during sub-nanosecond ESD events. Use Value: Limits clamping voltage to ≤12.5 V at 5 A, preventing latch-up or gate oxide damage in 3.3 V USB transceivers. |
Use Scenario: Shielding DVI TMDS clock and data channels from electrostatic discharge in flat-panel displays and graphics adapters. IC Role / Device Role / Timing Role: Low-capacitance transient suppressor mounted adjacent to DVI connector, referenced to chassis ground. Use Value: Maintains signal integrity with ≤5.0 pF I/O-to-GND capacitance while meeting IEC 61000-4-2 ±20 kV contact immunity. |
| Automotive Camera Link Protection | Industrial Monitor Interface Protection |
|
Use Scenario: Safeguarding MIPI D-PHY or LVDS video links from ESD in rear-view or surround-view camera modules. IC Role / Device Role / Timing Role: Unidirectional ESD array protecting differential pairs in automotive-grade video transmission paths. Use Value: AEC-Q101 qualification and −40 °C to +125 °C operation ensure robustness in vehicle cabin and exterior environments. |
Use Scenario: Securing VGA or DVI inputs on industrial HMIs and medical display panels exposed to frequent operator contact. IC Role / Device Role / Timing Role: Dual-line ESD suppressor installed at front-panel connector, referenced to system ground with minimal trace length. Use Value: UL 94 V-0 rating and 500 W peak power dissipation support safety-critical and long-lifecycle industrial deployments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5Z5.0T1G | Single-channel, SOD-523, 5.0 V VRWM, 14.5 V VC @ 5 A, 30 pF I/O–GND | Higher capacitance limits use to low-speed lines (≤10 Mbps); no dual-line integration | Select when space-constrained single-line protection is needed and USB/DVI speed is not required |
| TPD2E001DRYR | Two-channel, X2SON-6, 5.5 V VRWM, 12 V VC @ 5 A, 1.5 pF I/O–GND | Lower capacitance but lacks AEC-Q101 qualification and automotive temperature range | Prefer for consumer-grade high-speed interfaces where automotive qualification is unnecessary |
Compared with ESD5Z5.0T1G and TPD2E001DRYR, the NUP2201MR6T1G uniquely combines dual-line integration, AEC-Q101 compliance, and balanced 3–5 pF capacitance-making it optimal for automotive USB/DVI systems requiring both signal fidelity and ruggedized reliability.
Availability
NUP2201MR6T1G is available at Aetrix Electronics and suitable for USB 2.0 port protection, DVI interface hardening, and automotive camera link safeguarding requiring stable component supply across production lifecycles.
Supply support for NUP2201MR6T1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensor, and logic solutions for automotive, industrial, cloud, and consumer markets.
The NUP2201MR6T1G belongs to onsemi's ESD protection diode array product line, engineered specifically for high-speed digital interface protection where low capacitance, precise clamping, and automotive-grade reliability are mandatory.
FAQ
What is the maximum clamping voltage of the NUP2201MR6T1G under IEC 61000-4-2 ESD stress?
The NUP2201MR6T1G clamps to 12.5 V at 5 A and 20 V at 8 A under the 8×20 µs pulse waveform. For IEC 61000-4-2 contact discharge (±20 kV), oscilloscope screenshots in the official datasheet show peak clamping voltages below 18 V during positive and negative 8 kV events. This performance ensures compatibility with 3.3 V and 5 V interface ICs. The NUP2201MR6T1G achieves this via integrated steering diodes and a low-VF surge diode structure.
Can the NUP2201MR6T1G protect both data and power lines simultaneously?
Yes-the NUP2201MR6T1G supports simultaneous protection of two data lines (pins 1 and 6) and the VBUS or VCC line (via pin 5). When pin 5 is connected to the 5 V supply rail, the internal surge diode clamps overvoltage on that rail during transients, while steering diodes shunt ESD from data lines to VCC or ground. This dual-role capability eliminates the need for separate power-rail TVS devices in compact USB or DVI designs. The NUP2201MR6T1G's architecture inherently supports this integrated protection scheme.
Is the NUP2201MR6T1G suitable for automotive applications?
Yes-the NUP2201MR6T1G is AEC-Q101 qualified and PPAP capable, with guaranteed operation from −40 °C to +125 °C. It meets automotive ESD immunity requirements per ISO 10605 and system-level IEC 61000-4-2 testing. Its TSOP-6 package is validated for thermal cycling and mechanical shock in automotive environments. The NUP2201MR6T1G is explicitly recommended for infotainment USB ports, ADAS camera links, and display interfaces in production vehicles.
How does the NUP2201MR6T1G achieve low capacitance while maintaining high surge capability?
The NUP2201MR6T1G uses a monolithic silicon design that separates low-capacitance steering diodes (1.5–3.0 pF I/O-to-I/O) from a dedicated high-energy surge diode. This partitioning avoids the trade-off seen in single-diode TVS devices, where larger die size increases capacitance. The result is 3.0–5.0 pF I/O-to-GND capacitance alongside 500 W peak power dissipation. The NUP2201MR6T1G delivers this combination through proprietary process optimization and internal layout segmentation-not external component stacking.
What is the correct PCB layout practice for minimizing clamping voltage overshoot with the NUP2201MR6T1G?
To minimize clamping voltage overshoot, connect pin 2 (VN) directly to a solid ground plane using multiple vias, keep all traces to pins 1 and 6 shorter than 5 mm, and avoid stubs or right-angle bends. Place the NUP2201MR6T1G within 3 mm of the protected connector. Do not route sensitive signals under the device. These practices reduce parasitic inductance, which otherwise adds L·di/dt voltage spikes exceeding the intrinsic clamping level. The NUP2201MR6T1G's performance depends critically on this layout discipline-its datasheet specifies <1 nH ground loop inductance for rated VC.
NUP2201MR6T1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SOT-23-6 Thin, TSOT-23-6
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5V (Max)
- Voltage - Breakdown (Min):
- 6V
- Voltage - Clamping (Max) @ Ipp:
- 20V
- Current - Peak Pulse (10/1000µs):
- 8A (8/20µs)
- Power - Peak Pulse:
- 500W
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 3pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSOP
NUP2201MR6T1G FAQ
1.How can I place an order for NUP2201MR6T1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NUP2201MR6T1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NUP2201MR6T1G reliable?
The price and inventory of NUP2201MR6T1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NUP2201MR6T1G is usually 5 days.
3.What payment methods are accepted for NUP2201MR6T1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NUP2201MR6T1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NUP2201MR6T1G?
NUP2201MR6T1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NUP2201MR6T1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NUP2201MR6T1G?
For technical support, including NUP2201MR6T1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NUP2201MR6T1G requirements.
6.How does Aetrix verify that NUP2201MR6T1G is sourced from the original manufacturer or authorized distributors?
All NUP2201MR6T1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NUP2201MR6T1G meets industry standards.
7.What is the process for return or replacement of NUP2201MR6T1G?
All NUP2201MR6T1G units undergo pre-shipment inspection (PSI). If there is an issue with NUP2201MR6T1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NUP2201MR6T1G part is unused and in its original packaging.
Return procedure for NUP2201MR6T1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NUP2201MR6T1G Tags

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DESD3V3E1BL-7B
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ESD5Z3.3T1G
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D5V0H1B2LP-7B
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D5V0P1B2LP-7B
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DESD5V0U1BA-7
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ESD5Z5.0T1G
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DESD5V0U1BB-7
Diodes Incorporated

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D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
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