onsemi NUP4012PXV6T1G
- Part No.:
- NUP4012PXV6T1G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SOT-563, SOT-666
- Datasheet:
-
NUP4012PXV6T1G.pdf
- Description:
- TVS DIODE 4VWM 9.5VC SOT563
- Quantity:
- Payment:

- Shipping:

Inventory:4,049
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Product details
Overview
NUP4012PXV6T1G from onsemi is a quad unidirectional transient voltage suppressor array designed for ESD protection of high-speed data lines. It features 0.7 pF typical capacitance, 4.0 V working peak reverse voltage (VRWM), 5.2 V minimum breakdown voltage (VBR), and IEC 61000−4−2 Level 4 (±8 kV contact) compliance - deployed in USB 2.0 interfaces and SIM card circuits.
For engineers reviewing the NUP4012PXV6T1G datasheet, pinout, applications, or equivalent options, key selection criteria include ultra-low capacitance for signal integrity, common-anode SOT-563 packaging for space-constrained layouts, clamping voltage under 9.5 V at 1 A, and verified ESD survivability per IEC61000−4−2.
Technical Context
This device implements a common-anode quad unidirectional TVS architecture, where all four cathodes (D1–D4) connect to individual I/O lines and share a single anode terminal tied to ground. Each channel operates independently with identical electrical characteristics including VRWM = 4.0 V and VBR ≥ 5.2 V at IT = 1 mA.
It delivers fast response to ESD transients (sub-nanosecond), maintains ≤1.0 µA reverse leakage at VRWM, and achieves clamping voltage ≤9.5 V under 1 A 8/20 µs surge current - enabling protection without signal distortion in high-frequency digital interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Capacitance | 0.7 pF typical (line-to-GND @ 1 MHz); preserves signal integrity in USB 2.0 and high-speed serial links |
| VRWM | 4.0 V maximum (working peak reverse voltage); matches 3.3 V rail systems with margin |
| VBR | 5.2 V minimum @ 1 mA; ensures reliable turn-on before IC damage threshold |
| Clamping Voltage | ≤9.5 V @ IPP = 1 A (8/20 µs pulse); limits stress on protected transceivers |
| ESD Rating | IEC 61000−4−2 Level 4 (±8 kV contact); certified for end-equipment compliance |
| Leakage Current | ≤1.0 µA @ VRWM; avoids loading low-power I/O pins |
| Package | SOT-563 (1.6 mm × 1.2 mm × 0.55 mm); enables dense routing in mobile PCBs |
Pinout & Package
SOT-563 package: 6-pin, low-profile surface-mount case (1.60 mm × 1.20 mm × 0.55 mm), common-anode configuration with shared ground terminal.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Anode (Common) | Shared ground connection for all four diodes; must be connected to system GND |
| 2 | Cathode D1 | ESD protection path for first data line (e.g., USB D+) |
| 3 | Cathode D2 | ESD protection path for second data line (e.g., USB D−) |
| 4 | Cathode D3 | ESD protection path for third data line (e.g., SIM CLK) |
| 5 | Cathode D4 | ESD protection path for fourth data line (e.g., SIM I/O) |
| 6 | No Connect | Internally unused; left floating or unconnected on PCB |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low capacitance | 0.7 pF typical per channel - minimizes insertion loss and timing skew in >480 Mbps USB 2.0 links |
| Quad-line integration | Four independent ESD paths in one SOT-563 footprint - reduces board area vs. discrete diodes |
| Common-anode topology | Single ground pin simplifies layout and improves grounding consistency across protected lines |
| IEC61000−4−2 Level 4 rating | Validated ±8 kV contact discharge performance - meets end-product immunity requirements |
| Pb-free construction | RoHS-compliant SOT-563 package with matte tin lead finish - supports lead-free reflow assembly |
Applications
| USB 2.0 High-Speed Interface | SIM Card Protection |
|---|---|
Use Scenario: Protecting differential D+/D− lines in smartphone or tablet USB ports against user-handling ESD events. IC Role / Device Role / Timing Role: Unidirectional TVS array clamping transient overvoltage before it reaches the USB transceiver IC. Use Value: 0.7 pF capacitance prevents signal degradation at 480 Mbps; clamping ≤9.5 V ensures PHY-level safety. | Use Scenario: Shielding SIM card interface signals (CLK, I/O, RST, VCC) from electrostatic discharge during hot-swap insertion. IC Role / Device Role / Timing Role: Four-channel ESD suppressor with shared ground, placed adjacent to SIM connector pads. Use Value: Low leakage (≤1 µA) avoids battery drain; small SOT-563 footprint fits tight space near SIM socket. |
| Mobile Phone Front-End | MP3 Player Audio/Data Lines |
Use Scenario: Safeguarding touchscreen controller I²C lines and camera module data buses in slim smartphones. IC Role / Device Role / Timing Role: Common-anode quad TVS providing coordinated protection for multiple low-voltage peripherals. Use Value: 4.0 V VRWM aligns with 3.3 V I/O rails; 0.55 mm profile accommodates ultra-thin bezel designs. | Use Scenario: Protecting headphone jack detection, microSD interface, and button input lines in portable audio devices. IC Role / Device Role / Timing Role: Low-capacitance ESD clamp preventing latch-up or gate oxide damage in analog/digital mixed-signal ICs. Use Value: Sub-1 pF capacitance eliminates audible pop/click artifacts; ±8 kV rating covers consumer handling conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5Z3.3T5G | Single-channel, 3.3 V VRWM, 0.65 pF capacitance, SOD-523 package | Requires four separate placements; lacks integrated quad solution | Use when board layout allows discrete placement and lower VRWM is required |
| CM1213A-04SO | Quad-channel, 5.0 V VRWM, 0.8 pF capacitance, SOT-23-6 package | Larger footprint (2.9 mm × 1.3 mm), higher VRWM may reduce margin on 3.3 V lines | Prefer when existing design uses SOT-23-6 land pattern or requires higher VRWM headroom |
Compared with ESD5Z3.3T5G and CM1213A-04SO, the NUP4012PXV6T1G offers optimal balance of ultra-low capacitance, compact SOT-563 size, and 4.0 V VRWM tailored for 3.3 V I/O - making it superior for space- and signal-integrity-critical USB and SIM applications.
Availability
NUP4012PXV6T1G is available at Aetrix Electronics and suitable for USB 2.0 interface protection, SIM card circuit safeguarding, and mobile front-end ESD mitigation requiring stable component supply and RoHS-compliant sourcing.
Supply support for NUP4012PXV6T1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient power and signal management solutions, serving automotive, industrial, cloud, and consumer markets.
The NUP4012PXV6T1G belongs to onsemi's ESD protection diode product line, engineered specifically for ultra-low-capacitance, multi-line transient suppression in high-speed portable electronics interfaces.
FAQ
What is the clamping voltage of the NUP4012PXV6T1G under ESD stress?
The NUP4012PXV6T1G exhibits a clamping voltage of ≤9.5 V when subjected to a 1 A 8/20 µs surge current. Under IEC 61000−4−2 ±8 kV contact discharge, its actual clamping waveform remains below this limit throughout the pulse duration, as confirmed by oscilloscope screenshots in the official datasheet. This performance ensures downstream ICs see minimal overvoltage during real-world ESD events.
Is the NUP4012PXV6T1G suitable for USB 2.0 high-speed data lines?
Yes, the NUP4012PXV6T1G is explicitly validated for USB 2.0 high-speed interfaces due to its 0.7 pF typical capacitance per channel, which avoids signal integrity degradation at 480 Mbps. Its common-anode SOT-563 layout allows clean routing of D+ and D− lines with matched trace lengths, and its 4.0 V VRWM provides appropriate margin above the 3.3 V nominal bus voltage - all critical for reliable USB 2.0 operation.
Does the NUP4012PXV6T1G have a pin 6 connection?
No, pin 6 of the NUP4012PXV6T1G is a no-connect (NC) terminal. The device uses only five functional terminals: pin 1 (common anode), pins 2–5 (cathodes D1–D4), and pin 6 is internally unconnected. PCB layout must leave pin 6 floating or omit solder paste; connecting it may cause unintended current paths or violate the common-anode grounding scheme required for proper ESD clamping.
What is the maximum operating temperature range for the NUP4012PXV6T1G?
The NUP4012PXV6T1G supports an operating junction temperature range of −40 °C to +125 °C, as specified in its Absolute Maximum Ratings table. This wide thermal envelope enables deployment in mobile handsets, automotive infotainment modules, and industrial handhelds where ambient temperatures fluctuate significantly - provided PCB thermal design maintains junction temperature within this limit during sustained ESD events or high-current transients.
How does the common-anode configuration of the NUP4012PXV6T1G affect circuit design?
The common-anode configuration of the NUP4012PXV6T1G requires the anode (pin 1) to be tied directly to system ground, while each cathode (pins 2–5) connects to a separate protected I/O line. This topology ensures symmetrical clamping behavior across all channels and eliminates ground bounce between protected lines. Designers must avoid sharing this ground with noisy power planes and ensure low-inductance grounding to preserve sub-10 V clamping performance during fast ESD transients.
NUP4012PXV6T1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SOT-563, SOT-666
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Zener
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 4V (Max)
- Voltage - Breakdown (Min):
- 5.2V
- Voltage - Clamping (Max) @ Ipp:
- 9.5V
- Current - Peak Pulse (10/1000µs):
- 1A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.7pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-563
NUP4012PXV6T1G FAQ
1.How can I place an order for NUP4012PXV6T1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NUP4012PXV6T1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NUP4012PXV6T1G reliable?
The price and inventory of NUP4012PXV6T1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NUP4012PXV6T1G is usually 5 days.
3.What payment methods are accepted for NUP4012PXV6T1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NUP4012PXV6T1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NUP4012PXV6T1G?
NUP4012PXV6T1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NUP4012PXV6T1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NUP4012PXV6T1G?
For technical support, including NUP4012PXV6T1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NUP4012PXV6T1G requirements.
6.How does Aetrix verify that NUP4012PXV6T1G is sourced from the original manufacturer or authorized distributors?
All NUP4012PXV6T1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NUP4012PXV6T1G meets industry standards.
7.What is the process for return or replacement of NUP4012PXV6T1G?
All NUP4012PXV6T1G units undergo pre-shipment inspection (PSI). If there is an issue with NUP4012PXV6T1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NUP4012PXV6T1G part is unused and in its original packaging.
Return procedure for NUP4012PXV6T1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NUP4012PXV6T1G Tags

-
ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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