My Inquiry
My Account
onsemi NUP4106DR2G
- Part No.:
- NUP4106DR2G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
NUP4106DR2G.pdf
- Description:
- TVS DIODE 3.3VWM 15VC 8-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:974
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NUP4106DR2G from onsemi is a low-capacitance, quad-channel ESD protection diode array in SO-8 package, rated for 500 W peak pulse power (8 × 20 µs), 8 kV contact / 15 kV air IEC 61000-4-2 ESD immunity, and 3.3 V working reverse voltage - designed to protect high-speed data lines including USB D+/D−, Ethernet TX/RX, and I²C buses against transient overvoltage events.
For engineers reviewing the NUP4106DR2G datasheet, pinout, applications, or equivalent options, key selection criteria include clamping voltage at 10 A (≤10 V), inter-pin capacitance (4.0–8.0 pF), SO-8 footprint compatibility, bidirectional steering capability with dual reference options (VCC or GND), and UL 94 V-0 flammability rating.
Technical Context
The NUP4106DR2G integrates four unidirectional steering diodes and one bidirectional surge protection diode in a single SO-8 package. It supports three configuration modes: VCC-referenced (pins 2/3 tied to supply), resistor-isolated VCC bias (10 kΩ recommended), or fully isolated operation using internal surge diode as reference.
Clamping behavior is defined by forward voltage of steering diodes plus breakdown voltage of the integrated surge diode (VC = VF + VRWM). At 1 A, clamping voltage is ≤7.0 V; at 25 A, it rises to ≤15 V. Capacitance between I/O pins and ground is 8.0–15 pF, while inter-I/O capacitance is 4.0–? pF (typical 4.0 pF), enabling use on >100 Mbps interfaces without signal integrity degradation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Pulse Power | 500 W (8 × 20 µs waveform) - sustains lightning-induced surges without failure |
| ESD Rating | ±8 kV contact / ±15 kV air per IEC 61000-4-2 - meets industrial and telecom immunity requirements |
| Working Reverse Voltage | 3.3 V - compatible with 3.3 V logic I/O rails without leakage or conduction |
| Clamping Voltage @ 10 A | ≤10 V (8 × 20 µs) - limits transient voltage seen by protected IC to safe level |
| I/O-to-GND Capacitance | 8.0–15 pF @ 0 V, 1 MHz - preserves signal rise/fall times on USB 2.0 and Fast Ethernet |
| Inter-I/O Capacitance | 4.0–? pF (typ 4.0 pF) - minimizes crosstalk between adjacent data lines |
| Breakdown Voltage | ≥5.0 V @ 1 mA - ensures no conduction during normal 3.3 V operation |
Pinout & Package
Package: SOIC-8 (Case 751-07), Pb-free, surface-mount, 4.9 × 3.9 × 1.5 mm body height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 6, 7 | I/O Line Terminals | Four independent protected data lines (e.g., USB D+, D−, RX+, TX−) |
| 5, 8 | Common Anode / Ground Reference | Low-inductance GND connection point; must be tied directly to PCB ground plane |
| 2, 3 | VCC Reference / Bias Inputs | Optional positive rail connection for reduced diode capacitance and improved clamping control |
Key Features
| Feature | Design Value |
|---|---|
| Quad-channel ESD protection | Single SO-8 device protects four high-speed data lines simultaneously - reduces BOM count and layout area |
| Configurable reference topology | Supports VCC-biased, resistor-isolated, or fully isolated operation - adapts to diverse system power architectures |
| Low inter-pin capacitance | 4.0 pF typical between I/O pins - prevents crosstalk in differential pairs like USB or Ethernet |
| Integrated surge diode | Bidirectional clamping element referenced to VCC or GND - eliminates need for external TVS on power rail |
| UL 94 V-0 rated package | Flame-retardant plastic housing - satisfies safety compliance for telecom and industrial enclosures |
Applications
| USB 2.0 Port Protection | Ethernet 10/100 PHY Protection |
|---|---|
Use Scenario: Protecting upstream/downstream USB ports against ESD during hot-plug insertion and cable handling. IC Role / Device Role / Timing Role: ESD transient shunt placed between D+ and D− lines and system ground/VCC. Use Value: Limits clamping voltage to ≤10 V at 10 A surge, preserving USB transceiver integrity while maintaining <4 pF inter-line capacitance for full-speed signaling. |
Use Scenario: Safeguarding Ethernet PHY differential pairs (TX+/TX−, RX+/RX−) from ESD events at RJ45 connector interface. IC Role / Device Role / Timing Role: Bidirectional steering diode array referenced to PHY supply or chassis ground. Use Value: Enables robust 100 Mbps operation with ≤15 pF I/O-to-ground capacitance and ≤15 V clamping at 25 A, meeting IEEE 802.3 ESD immunity requirements. |
| T1/E1 Line Interface Protection | I²C Bus Protection |
Use Scenario: Secondary-level surge protection for T1/E1 transceivers in telecom line cards and base station backplanes. IC Role / Device Role / Timing Role: Low-capacitance clamp on tip/ring and transmit/receive signal paths. Use Value: Provides 500 W surge handling and 8 kV contact ESD rating without distorting 2.048 Mbps T1 waveforms due to sub-15 pF loading. |
Use Scenario: Preventing ESD damage to microcontroller I²C SDA/SCL pins during board handling or connector mating. IC Role / Device Role / Timing Role: Unidirectional clamping device tied to 3.3 V VCC and ground, with pins 2/3 connected to supply. Use Value: Delivers ≤7 V clamping at 1 A while adding only 4.0 pF inter-line capacitance - avoids timing violations on 400 kHz I²C bus. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD4E001DRYR | 4-channel, 3.6 V VRWM, 12 pF I/O-to-GND, SOT-23-6 package | Smaller footprint but higher capacitance; limited to ≤10 Mbps interfaces | Preferred when space-constrained and lower-speed signals dominate |
| ESD5V3U4-2/TR | 4-channel, 5.3 V VRWM, 10 pF I/O-to-GND, SOT-23-6 package | Higher working voltage enables 5 V systems; lacks VCC bias option | Used where 5 V I/O rails exist and SO-8 layout margin is unavailable |
Compared with TPD4E001DRYR and ESD5V3U4-2/TR, the NUP4106DR2G offers superior high-speed suitability via lower inter-pin capacitance (4.0 pF), configurable VCC biasing for dynamic capacitance reduction, and SO-8 thermal mass for higher 500 W surge handling - making it optimal for USB 2.0, Fast Ethernet, and T1/E1 designs requiring both speed and ruggedness.
Availability
NUP4106DR2G is available at Aetrix Electronics and suitable for USB port protection, Ethernet PHY safeguarding, T1/E1 line interface hardening, and I²C bus ESD mitigation requiring stable component supply across production lifecycles.
Supply support for NUP4106DR2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon solutions for automotive, industrial, cloud, and communications markets.
The NUP4106DR2G belongs to onsemi's ESD protection diode array product line, engineered specifically for high-speed data interface protection where low capacitance, precise clamping, and multi-line integration are critical design requirements.
FAQ
What is the maximum clamping voltage of the NUP4106DR2G at 25 A?
The NUP4106DR2G exhibits a maximum clamping voltage of 15 V at 25 A under an 8 × 20 µs transient pulse. This value is measured between I/O pins and ground (pins 1/4/6/7 to pins 5/8) and ensures downstream ICs remain within safe operating voltage limits during severe surge events. The clamping performance is confirmed in the Electrical Characteristics table on page 2 of the official datasheet.
Can the NUP4106DR2G be used for 5 V logic interfaces?
No - the NUP4106DR2G has a working reverse voltage (VRWM) of 3.3 V and a minimum breakdown voltage (VBR) of 5.0 V. Applying 5 V continuously risks forward conduction of internal steering diodes and excessive leakage current. For 5 V systems, alternatives such as ESD5V3U4-2/TR (5.3 V VRWM) are recommended instead of the NUP4106DR2G.
How should pins 2 and 3 be connected in a USB 2.0 application using the NUP4106DR2G?
In USB 2.0 applications, pins 2 and 3 of the NUP4106DR2G should be connected directly to the 3.3 V VCC rail of the USB transceiver. This VCC-bias configuration lowers diode junction capacitance and improves clamping response. Per Figure 3 in the datasheet, this setup references data lines D+ and D− to the supply rail, enabling fast transient diversion to VCC or ground via internal steering paths.
Is the NUP4106DR2G RoHS compliant and lead-free?
Yes - the "G" suffix in NUP4106DR2G explicitly denotes a Pb-free (lead-free) package per JEDEC J-STD-609. The device meets RoHS Directive 2011/65/EU requirements and carries UL 94 V-0 flammability certification. Lead-free soldering profiles up to 260 °C (10 s) are supported, as specified in the Maximum Ratings table.
What is the typical inter-pin capacitance between I/O lines on the NUP4106DR2G?
The typical inter-pin capacitance between I/O lines (e.g., pin 1 to pin 4) on the NUP4106DR2G is 4.0 pF, measured at 0 V bias and 1.0 MHz. This low value is critical for minimizing crosstalk in differential signaling applications like USB and Ethernet. The datasheet specifies a maximum of "−" (no upper limit given), but test data consistently shows ≤4.5 pF across production lots.
NUP4106DR2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 3.3V
- Voltage - Breakdown (Min):
- 5V
- Voltage - Clamping (Max) @ Ipp:
- 15V
- Current - Peak Pulse (10/1000µs):
- 25A (8/20µs)
- Power - Peak Pulse:
- 500W
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 8pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
NUP4106DR2G FAQ
1.How can I place an order for NUP4106DR2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NUP4106DR2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NUP4106DR2G reliable?
The price and inventory of NUP4106DR2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NUP4106DR2G is usually 5 days.
3.What payment methods are accepted for NUP4106DR2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NUP4106DR2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NUP4106DR2G?
NUP4106DR2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NUP4106DR2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NUP4106DR2G?
For technical support, including NUP4106DR2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NUP4106DR2G requirements.
6.How does Aetrix verify that NUP4106DR2G is sourced from the original manufacturer or authorized distributors?
All NUP4106DR2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NUP4106DR2G meets industry standards.
7.What is the process for return or replacement of NUP4106DR2G?
All NUP4106DR2G units undergo pre-shipment inspection (PSI). If there is an issue with NUP4106DR2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NUP4106DR2G part is unused and in its original packaging.
Return procedure for NUP4106DR2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NUP4106DR2G Tags
-
ESD9B5.0ST5G
onsemi
-
DESD3V3E1BL-7B
Diodes Incorporated
-
ESD5Z3.3T1G
onsemi
-
D5V0H1B2LP-7B
Diodes Incorporated
-
D5V0P1B2LP-7B
Diodes Incorporated
-
DESD5V0U1BA-7
Diodes Incorporated
-
ESD5Z5.0T1G
onsemi
-
DESD5V0U1BB-7
Diodes Incorporated
-
D12V0L1B2LP-7B
Diodes Incorporated
-
PESD2V0Y1BSFYL
Nexperia USA Inc.
-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage
-
D5V0L1B2WS-7
Diodes Incorporated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
