onsemi NUP4114UPXV6T1G
- Part No.:
- NUP4114UPXV6T1G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SOT-563, SOT-666
- Datasheet:
-
NUP4114UPXV6T1G.pdf
- Description:
- TVS DIODE 5.5VWM 10VC SOT563
- Quantity:
- Payment:

- Shipping:

Inventory:22,980
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Product details
Overview
NUP4114UPXV6T1G from onsemi is a unidirectional ESD protection diode array designed for high-speed data line protection in USB 2.0, HDMI, and LVDS interfaces. It delivers 5.5 V working peak reverse voltage, <0.6 pF typical junction capacitance (I/O to GND), ±8 kV IEC 61000-4-2 contact ESD rating, 8.3 V clamping voltage at 1 A pulse, and operates from −40 °C to +125 °C.
For engineers reviewing the NUP4114UPXV6T1G datasheet, pinout, applications, or equivalent options, key selection criteria include ultra-low capacitance for signal integrity, low clamping voltage for IC-level transient suppression, IEC 61000-4-2 Level 4 compliance, SOT-563 package footprint compatibility, and integrated four-channel steering diode architecture with dedicated ground and VCC reference pins.
Technical Context
The NUP4114UPXV6T1G integrates four unidirectional steering diodes and one bidirectional ESD clamp in a single SOT-563 package. Its internal topology routes transients from I/O pins (1, 3, 4, 6) either to VCC (pin 5) or GND (pin 2), depending on polarity and configuration mode.
It supports three protection configurations: VCC-referenced (pin 5 connected), resistor-isolated (10 kΩ between pin 5 and VCC), or fully isolated (pin 5 open). Clamping behavior is defined by forward voltage of steering diodes plus ESD diode breakdown, not fixed rail voltage alone.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Working Peak Reverse Voltage | 5.5 V - Maximum continuous DC or RMS voltage the diodes withstand without conduction. |
| Junction Capacitance (I/O to GND) | 0.6 pF typical - Ensures minimal signal distortion on USB 2.0 and HDMI differential pairs. |
| Clamping Voltage @ 1 A | 8.3 V - Peak voltage seen by protected IC during 1 A ESD pulse; critical for sub-10 V logic safety. |
| IEC 61000-4-2 Contact ESD | ±8 kV - Meets industrial and consumer system-level immunity requirements per Level 4. |
| Operating Temperature Range | −40 °C to +125 °C - Qualified for automotive under-hood and industrial edge applications. |
| Response Time | <1.0 ns - Fast enough to suppress nanosecond-scale ESD transients before IC damage occurs. |
Pinout & Package
SOT-563 package (Case 463A), 1.60 mm × 1.20 mm × 0.55 mm body, 0.50 mm pitch, Pb-free, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O 1 | Protected high-speed data line input/output; routed to GND or VCC via internal steering diode. |
| 2 | GND | Dedicated low-inductance ground reference; must connect directly to PCB ground plane. |
| 3 | I/O 2 | Second protected data line; shares same clamping architecture as Pin 1. |
| 4 | I/O 3 | Third protected data line; enables compact 4-line protection in single 6-pin package. |
| 5 | VCC | Positive supply reference; enables lower-capacitance biasing and power-rail ESD protection. |
| 6 | I/O 4 | Fourth protected data line; completes quad-channel ESD protection capability. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low I/O-to-GND capacitance | 0.6 pF typical - Preserves signal rise/fall times in >480 Mbps USB 2.0 links. |
| Integrated VCC-referenced steering | Reduces effective capacitance vs. ground-only schemes and enables power-rail overvoltage protection. |
| Four independent data line channels | Single-device protection for full USB 2.0 interface (D+, D−, ID, VBUS sense) or dual LVDS pairs. |
| AEC-Q101 qualified | Validated for automotive electronics including infotainment and ADAS sensor interfaces. |
| Pb-free, Halogen-free, RoHS compliant | Meets global environmental compliance mandates without performance trade-offs. |
Applications
| USB 2.0 High-Speed Interface | HDMI/DVI Data Lines |
|---|---|
|
Use Scenario: Protecting D+ and D− lines in portable USB host/device ports against user-handling ESD events. IC Role / Device Role / Timing Role: ESD transient shunt placed immediately adjacent to connector, clamping fast-rising pulses before reaching USB transceiver. Use Value: Prevents latch-up or gate oxide damage in USB PHY ICs while maintaining <100 ps signal delay due to 0.6 pF loading. |
Use Scenario: Shielding TMDS clock and data channels in flat-panel display interconnects from cable-discharge events. IC Role / Device Role / Timing Role: Low-capacitance steering diode array referenced to local VCC, suppressing ±8 kV contact discharges without degrading 165 MHz pixel clock integrity. Use Value: Enables robust HDMI 1.4 compliance in monitors and docking stations without adding series impedance or equalization overhead. |
| LVDS Camera Interfaces | Notebook Internal Data Buses |
|
Use Scenario: Safeguarding high-speed serial links between image sensors and SoCs in automotive rear-view cameras. IC Role / Device Role / Timing Role: Quad-channel ESD clamp on LVDS differential pairs (CLK±, DATA±), operating across −40 °C to +125 °C ambient. Use Value: Maintains <5 mV common-mode noise margin and sub-100 ps skew across temperature while meeting ISO 10605 150 pF/2 kV requirements. |
Use Scenario: Protecting eDP, PCIe Gen1, or SATA lanes inside thin-client notebooks where board space limits discrete protection. IC Role / Device Role / Timing Role: Single SOT-563 device covering four critical high-speed traces, minimizing trace length to GND/VCC reference planes. Use Value: Reduces BOM count by 75% vs. four individual 0201 diodes while improving layout-controlled clamping consistency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD5V3U2U-2/TR | 0.5 pF capacitance, 5.3 V working voltage, ±12 kV air discharge, SOT-23-3 package (2-channel only). | Limited to dual-line protection; lacks VCC reference pin and quad-channel integration. | Choose when only two lines require protection and lowest possible capacitance is prioritized over channel count. |
| TPD2EUSB30DRYR | 0.7 pF capacitance, 5.5 V working voltage, ±12 kV contact ESD, 6-pin X2SON package, USB 3.0 optimized. | Designed for SuperSpeed (5 Gbps) signaling; higher capacitance unsuitable for strict USB 2.0 timing budgets. | Prefer for new USB 3.0 designs; avoid for legacy USB 2.0 systems requiring sub-0.65 pF loading. |
Compared with ESD5V3U2U-2/TR and TPD2EUSB30DRYR, the NUP4114UPXV6T1G uniquely balances quad-channel integration, 0.6 pF loading, and VCC-referenced clamping-making it optimal for space-constrained USB 2.0, HDMI, and LVDS systems needing coordinated multi-line protection without sacrificing signal fidelity.
Availability
NUP4114UPXV6T1G is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI/DVI display interconnects, and automotive LVDS camera links requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for NUP4114UPXV6T1G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient silicon solutions for automotive, industrial, cloud, medical, and IoT applications.
The NUP4114UPXV6T1G belongs to onsemi's ESD Protection Diode family, engineered specifically to replace discrete TVS arrays in high-speed digital interfaces where capacitance, clamping voltage, and layout efficiency are critical.
FAQ
What is the maximum clamping voltage of the NUP4114UPXV6T1G during an 8 kV IEC 61000-4-2 contact ESD event?
The NUP4114UPXV6T1G exhibits an ESD clamping voltage of approximately 8–10 V during ±8 kV IEC 61000-4-2 contact discharge, as verified by oscilloscope waveform screenshots in the official datasheet. This value reflects the actual voltage measured across the device terminals during the transient, not a theoretical limit. The clamping level remains consistent across temperature and ensures safe operation for 5 V logic interfaces. NUP4114UPXV6T1G achieves this via low-forward-voltage steering diodes combined with a dedicated ESD clamp structure.
Can the NUP4114UPXV6T1G be used to protect both data lines and power rails simultaneously?
Yes - the NUP4114UPXV6T1G supports simultaneous data line and power rail protection through its configurable pin 5 (VCC). When pin 5 is connected to the local supply rail, the internal steering diodes route positive transients to VCC and negative transients to GND (pin 2), thereby protecting both the data path and the power domain. This eliminates the need for separate power-rail TVS devices. NUP4114UPXV6T1G's design explicitly targets this dual-role use case, as confirmed in the Applications Information section of the datasheet.
Is the NUP4114UPXV6T1G compatible with automated SMT assembly processes?
Yes - the NUP4114UPXV6T1G uses the standard SOT-563 package (Case 463A), which is fully compatible with industry-standard pick-and-place equipment and reflow profiles. It is rated for lead solder temperature up to 260 °C for 10 seconds and conforms to JEDEC J-STD-020 moisture sensitivity level (MSL) 1. The device ships in 4000-unit tape-and-reel format (EIA-481 compliant), enabling seamless integration into high-volume manufacturing. NUP4114UPXV6T1G's Pb-free, RoHS-compliant finish further ensures process compatibility with modern lead-free soldering.
Does the NUP4114UPXV6T1G require external biasing components for basic operation?
No - the NUP4114UPXV6T1G operates without external biasing components in its default ground-referenced configuration (pin 5 left open or tied to VCC directly). However, a 10 kΩ isolation resistor between pin 5 and VCC is recommended when power supply noise isolation is required. All essential protection functionality - including 5.5 V reverse standoff, 0.6 pF capacitance, and ±8 kV ESD rating - is intrinsic to the device and does not depend on external passive components. NUP4114UPXV6T1G's integrated architecture eliminates the need for discrete RC networks or additional diodes.
How does the pinout of the NUP4114UPXV6T1G differ from other packages in the NUP4114 series?
The NUP4114UPXV6T1G uses the SOT-563 package with pin 1 = I/O 1, pin 2 = GND, pin 3 = I/O 2, pin 4 = I/O 3, pin 5 = VCC, pin 6 = I/O 4 - matching Style 12 in onsemi's generic TSOP-6/SOT-563 pinout documentation. This differs from the SC-88 (NUP4114UCLW1T1G) and TSOP-6 (NUP4114HMR6T1G) variants, which share identical signal assignments but incompatible footprints. NUP4114UPXV6T1G's SOT-563 layout enables denser routing than SC-88 and smaller board area than TSOP-6, while retaining full functional equivalence across the series.
NUP4114UPXV6T1G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SOT-563, SOT-666
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 5.5V
- Voltage - Clamping (Max) @ Ipp:
- 10V
- Current - Peak Pulse (10/1000µs):
- 8A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.6pF @ 1MHz
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-563
NUP4114UPXV6T1G FAQ
1.How can I place an order for NUP4114UPXV6T1G through Aetrix?
Please submit a Request for Quotation (RFQ) for NUP4114UPXV6T1G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NUP4114UPXV6T1G reliable?
The price and inventory of NUP4114UPXV6T1G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NUP4114UPXV6T1G is usually 5 days.
3.What payment methods are accepted for NUP4114UPXV6T1G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NUP4114UPXV6T1G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NUP4114UPXV6T1G?
NUP4114UPXV6T1G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NUP4114UPXV6T1G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NUP4114UPXV6T1G?
For technical support, including NUP4114UPXV6T1G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NUP4114UPXV6T1G requirements.
6.How does Aetrix verify that NUP4114UPXV6T1G is sourced from the original manufacturer or authorized distributors?
All NUP4114UPXV6T1G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NUP4114UPXV6T1G meets industry standards.
7.What is the process for return or replacement of NUP4114UPXV6T1G?
All NUP4114UPXV6T1G units undergo pre-shipment inspection (PSI). If there is an issue with NUP4114UPXV6T1G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NUP4114UPXV6T1G part is unused and in its original packaging.
Return procedure for NUP4114UPXV6T1G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NUP4114UPXV6T1G Tags

-
ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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