onsemi NUP4114UPXV6T2G
- Part No.:
- NUP4114UPXV6T2G
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SOT-563, SOT-666
- Datasheet:
-
NUP4114UPXV6T2G.pdf
- Description:
- TVS DIODE 5.5VWM 10VC SOT563
- Quantity:
- Payment:

- Shipping:

Inventory:5,476
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Product details
Overview
NUP4114UPXV6T2G from onsemi is a unidirectional ESD protection diode array designed for high-speed data line protection in USB 2.0, HDMI, and LVDS interfaces. It delivers 5.5 V working peak reverse voltage, <0.6 pF typical I/O-to-GND capacitance, ±8 kV IEC 61000-4-2 contact ESD immunity, 8.3–10 V clamping voltage at 1–8 A pulse current, and operates across −40°C to +125°C junction temperature.
For engineers reviewing the NUP4114UPXV6T2G datasheet, pinout, applications, or equivalent options, key selection criteria include ultra-low capacitance for signal integrity, low clamping voltage for IC-level transient suppression, TSOP-6 package compatibility with high-density PCB layouts, and AEC-Q101 qualification for automotive-grade reliability.
Technical Context
The NUP4114UPXV6T2G integrates four steering diodes and one bidirectional ESD clamp in a single TSOP-6 package. Its internal configuration routes transients from I/O pins (1, 3, 4, 6) to either ground (pin 2) or VCC (pin 5), enabling flexible reference options including direct VCC biasing, isolated resistor-biased, or fully floating operation using the internal ESD diode as reference.
It employs fast-switching silicon diode technology with <1.0 ns response time and supports nonrepetitive 8/20 µs pulse waveforms up to 12 A peak current. The device's clamping behavior is defined per IEC 61000-4-2 test conditions, with measured ESD clamping voltage captured via oscilloscope waveform screenshots-not inferred from static DC parameters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Working Peak Reverse Voltage | 5.5 V - Maximum continuous DC or RMS voltage the diodes withstand without conduction on data lines. |
| Junction Capacitance (I/O to GND) | 0.6 pF typical - Enables minimal signal distortion on USB 2.0 (480 Mbps) and HDMI TMDS channels. |
| Clamping Voltage @ 1 A | 8.3–10 V - Limits transient overvoltage seen by protected ICs during ESD events, preserving logic-level integrity. |
| ESD Immunity (IEC 61000-4-2) | ±8 kV contact - Meets Level 4 industrial and automotive system-level ESD compliance requirements. |
| Operating Junction Temperature | −40°C to +125°C - Supports deployment in under-hood automotive modules and industrial edge controllers. |
| Package | TSOP-6 (Case 318G, 3.00 × 1.50 × 0.90 mm) - Surface-mount footprint compatible with automated SMT assembly and thermal management in compact designs. |
| Leakage Current @ VRWM | 1.0 µA max - Prevents measurable DC loading on high-impedance data lines such as LVDS receivers. |
Pinout & Package
TSOP-6 package (Case 318G, 3.00 × 1.50 × 0.90 mm, 0.95 mm pitch), Pb-free, RoHS compliant, AEC-Q101 qualified.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O Line 1 | Protected high-speed data input/output; connected to USB D+, HDMI TMDS+, or LVDS+. |
| 2 | Ground Reference | Low-inductance return path for ESD current; must connect directly to solid ground plane. |
| 3 | I/O Line 2 | Second protected data line; used for differential pair complement (e.g., USB D−, LVDS−). |
| 4 | I/O Line 3 | Third independent data line; supports multi-lane interfaces like DVI or parallel camera buses. |
| 5 | VCC Reference | Optional positive rail connection for biasing steering diodes; reduces capacitance and improves clamping symmetry. |
| 6 | I/O Line 4 | Fourth protected line; enables full-port protection for quad-data applications (e.g., MIPI D-PHY lanes). |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low I/O-to-GND capacitance | 0.6 pF typical - Preserves signal rise/fall times and minimizes bit error rate in 480 Mbps USB 2.0 links. |
| Low clamping voltage at 1 A | 8.3 V typical - Keeps transient voltage below 10 V, protecting 3.3 V and 5 V logic interfaces without additional TVS stages. |
| Sub-1 ns response time | <1.0 ns - Activates before sensitive transceiver circuitry sustains damage during nanosecond-scale ESD pulses. |
| AEC-Q101 qualification | Qualified for automotive electronics - Validated for temperature cycling, humidity, mechanical shock, and ESD robustness per automotive standards. |
| Integrated 4-line + power rail protection | Single TSOP-6 package protects four data lines and optionally the VCC rail - Reduces BOM count vs. discrete diode solutions. |
Applications
| USB 2.0 High-Speed Interface | HDMI/DVI Digital Video |
|---|---|
|
Use Scenario: Protecting USB 2.0 D+/D− differential pairs on host controllers and peripheral devices against user-handling ESD events. IC Role / Device Role / Timing Role: ESD transient suppressor placed immediately at connector entry point, routing surges to GND or VCC before reaching PHY layer. Use Value: Maintains 480 Mbps data integrity with <0.6 pF loading and clamps transients to ≤10 V, preventing PHY latch-up or I/O damage. |
Use Scenario: Shielding HDMI TMDS+ and TMDS− channels in flat-panel displays, set-top boxes, and graphics cards from cable-discharge events. IC Role / Device Role / Timing Role: Low-capacitance steering diode array referenced to local ground, suppressing ESD-induced jitter and pixel corruption. Use Value: Enables clean 165 MHz TMDS signaling with sub-1 ns response and no measurable insertion loss due to 0.6 pF I/O capacitance. |
| LVDS Display Interfaces | Automotive Infotainment Systems |
|
Use Scenario: Safeguarding LVDS clock/data pairs in notebook displays and industrial HMIs where long flex cables increase ESD coupling risk. IC Role / Device Role / Timing Role: Unidirectional ESD clamp on each LVDS lane, referenced to local ground to avoid common-mode disruption. Use Value: Ensures stable 600+ Mbps LVDS eye diagrams with <10 V clamping and zero added jitter-critical for timing-critical display timing controllers. |
Use Scenario: Protecting USB, HDMI, and camera interface ports in automotive head units and ADAS domain controllers exposed to harsh ESD environments. IC Role / Device Role / Timing Role: AEC-Q101-qualified ESD array providing system-level ESD resilience without derating or external filtering. Use Value: Delivers guaranteed ±8 kV contact/±15 kV air ESD immunity while operating reliably from −40°C to +125°C junction temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD4E05U06DQAR | 0.5 pF typical capacitance; 5.5 V VRWM; ±12 kV contact ESD rating; 6-pin SON package (1.45 × 1.0 mm). | Better suited for space-constrained mobile designs; lower profile but less thermal mass than TSOP-6. | Select when board area is critical and thermal dissipation requirements are moderate. |
| ESD5451N | 0.35 pF typical I/O-to-GND capacitance; 5.0 V VRWM; ±8 kV contact; SOT-563 package (1.6 × 1.2 mm). | Lower capacitance ideal for >1 Gbps interfaces (e.g., USB 3.0 SS); reduced clamping margin (7.5 V @ 1 A). | Prefer for next-gen high-speed interfaces where signal fidelity outweighs absolute clamping voltage. |
Compared with TPD4E05U06DQAR and ESD5451N, the NUP4114UPXV6T2G offers superior thermal robustness in TSOP-6, balanced clamping performance for 480 Mbps–1 Gbps applications, and automotive qualification-making it optimal for industrial and automotive USB/HDMI endpoints where reliability and layout flexibility matter more than minimal footprint.
Availability
NUP4114UPXV6T2G is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI/DVI video port hardening, and automotive infotainment system design requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for NUP4114UPXV6T2G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor manufacturer specializing in energy-efficient power, analog, sensor, and logic solutions for automotive, industrial, cloud, and consumer markets.
The NUP4114UPXV6T2G belongs to onsemi's ESD Protection Diode family, engineered specifically for high-speed digital interface protection where ultra-low capacitance, precise clamping, and automotive-grade reliability are mandatory.
FAQ
What is the primary function of the NUP4114UPXV6T2G?
The NUP4114UPXV6T2G is a unidirectional ESD protection diode array that safeguards high-speed data lines-including USB 2.0, HDMI, and LVDS-from electrostatic discharge events. It uses integrated steering diodes and an ESD clamp to divert transients to ground or VCC, limiting voltage seen by downstream ICs to ≤10 V while adding only 0.6 pF capacitance per I/O line. This ensures signal integrity and interface reliability without compromising speed.
Which package does the NUP4114UPXV6T2G use, and why does it matter?
The NUP4114UPXV6T2G uses the TSOP-6 package (Case 318G, 3.00 × 1.50 × 0.90 mm). This package provides better thermal dissipation and mechanical robustness than smaller alternatives like SOT-563, making it suitable for automotive and industrial applications where sustained pulse handling and board-level reliability are critical. Its 0.95 mm lead pitch supports standard SMT reflow processes while maintaining low parasitic inductance for effective ESD suppression.
How does the NUP4114UPXV6T2G achieve low clamping voltage?
The NUP4114UPXV6T2G achieves low clamping voltage-8.3 V typical at 1 A-through optimized silicon diode design and integrated ESD clamp topology. During an ESD event, current flows through fast-steering diodes into the dedicated ESD diode, producing a combined forward drop (VF) plus ESD diode voltage (VESD). This architecture avoids the higher clamping voltages typical of discrete TVS diodes, ensuring protected ICs remain within safe operating limits even during ±8 kV contact discharges.
Is the NUP4114UPXV6T2G suitable for automotive applications?
Yes, the NUP4114UPXV6T2G is AEC-Q101 qualified and PPAP capable, meeting automotive-grade stress testing requirements for temperature cycling, humidity, mechanical shock, and ESD. Its −40°C to +125°C operating junction temperature range, Pb-free/RoHS compliance, and validated ±8 kV IEC 61000-4-2 contact immunity make it appropriate for infotainment systems, camera modules, and USB/HDMI ports in vehicles. onsemi provides full automotive documentation and traceability support.
Can the NUP4114UPXV6T2G protect both data lines and power rails simultaneously?
Yes-the NUP4114UPXV6T2G supports dual-role protection. Pins 1, 3, 4, and 6 protect four independent data lines; pin 5 connects to VCC to enable power-rail clamping via the internal ESD diode, while pin 2 serves as the low-inductance ground reference. When pin 5 is left open, the device operates in fully isolated mode using only the internal ESD diode as reference. This flexibility allows it to protect both signal integrity and power supply stability in a single component.
NUP4114UPXV6T2G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SOT-563, SOT-666
- Series:
- NUP4114
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V (Max)
- Voltage - Breakdown (Min):
- 5.5V
- Voltage - Clamping (Max) @ Ipp:
- 10V
- Current - Peak Pulse (10/1000µs):
- 12A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- Yes
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 0.6pF @ 1MHz (Max)
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-563
NUP4114UPXV6T2G FAQ
1.How can I place an order for NUP4114UPXV6T2G through Aetrix?
Please submit a Request for Quotation (RFQ) for NUP4114UPXV6T2G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NUP4114UPXV6T2G reliable?
The price and inventory of NUP4114UPXV6T2G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NUP4114UPXV6T2G is usually 5 days.
3.What payment methods are accepted for NUP4114UPXV6T2G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NUP4114UPXV6T2G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NUP4114UPXV6T2G?
NUP4114UPXV6T2G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NUP4114UPXV6T2G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NUP4114UPXV6T2G?
For technical support, including NUP4114UPXV6T2G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NUP4114UPXV6T2G requirements.
6.How does Aetrix verify that NUP4114UPXV6T2G is sourced from the original manufacturer or authorized distributors?
All NUP4114UPXV6T2G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NUP4114UPXV6T2G meets industry standards.
7.What is the process for return or replacement of NUP4114UPXV6T2G?
All NUP4114UPXV6T2G units undergo pre-shipment inspection (PSI). If there is an issue with NUP4114UPXV6T2G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NUP4114UPXV6T2G part is unused and in its original packaging.
Return procedure for NUP4114UPXV6T2G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NUP4114UPXV6T2G Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

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D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

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PESD2V0Y1BSFYL
Nexperia USA Inc.

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DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

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D5V0L1B2WS-7
Diodes Incorporated
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