onsemi NUP4304MR6T1
- Part No.:
- NUP4304MR6T1
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SC-74, SOT-457
- Datasheet:
-
NUP4304MR6T1.pdf
- Description:
- TVS DIODE SC74-6
- Quantity:
- Payment:

- Shipping:

Inventory:7,459
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Product details
Overview
NUP4304MR6T1 from onsemi is a low-capacitance ESD protection diode array for four high-speed data lines, featuring 1.5 pF max I/O-to-I/O capacitance, 70 V reverse voltage rating, and compliance with IEC61000−4−2 Level 4 (8 kV contact / 15 kV air); used in USB 2.0, I²C, and telecom secondary IC protection.
For engineers reviewing the NUP4304MR6T1 datasheet, pinout, applications, or equivalent options, key selection criteria include clamping behavior under ESD transients, I/O-to-ground capacitance (max 3.0 pF), thermal resistance (556 °C/W), and TSOP-6 package compatibility with high-density PCB layouts.
Technical Context
The NUP4304MR6T1 integrates eight steering diodes in a single TSOP-6 package to protect four bidirectional data lines-each line uses two back-to-back diodes referenced to either VCC (pin 2) or ground (pin 5). It operates without external bias in Option 4 or with VCC bias in Options 1–3 to reduce diode capacitance.
Clamping action routes transient current to VCC or GND depending on polarity; forward voltage is 1.25 V at 150 mA, and leakage remains ≤50 µA at 70 V and 150°C. The device meets JEDEC JESD22 Class 3B (HBM) and Class C (MM) ESD standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Capacitance (I/O to I/O) | Max 1.5 pF at 0 V, 1 MHz - preserves signal integrity on USB 2.0 and I²C buses |
| Capacitance (I/O to GND) | Max 3.0 pF at 0 V, 1 MHz - limits loading on high-speed data lines |
| Reverse Voltage (VR) | 70 VDC - supports operation in 3.3 V and 5 V systems with margin |
| ESD Rating (IEC61000−4−2) | ±8 kV contact / ±15 kV air - meets industrial and peripheral interface immunity requirements |
| Forward Voltage (IF = 150 mA) | 1.25 V - ensures low clamping voltage during surge events |
| Junction Temperature Range | −40°C to +85°C - suitable for commercial and extended-temperature embedded applications |
| Thermal Resistance (RJA) | 556 °C/W - requires careful PCB copper area design for sustained surge handling |
Pinout & Package
Package: TSOP-6 (Case 318F), surface-mount, lead-free compatible, 3.0 × 1.5 × 0.95 mm body height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | I/O Line 1 | Protected bidirectional data line; connected internally to cathode of D1 and anode of D5 |
| 2 | VCC Reference | Bias supply input for reducing diode capacitance; optional in unbiased configurations |
| 3 | I/O Line 2 | Protected bidirectional data line; connected internally to cathode of D2 and anode of D6 |
| 4 | I/O Line 3 | Protected bidirectional data line; connected internally to cathode of D3 and anode of D7 |
| 5 | GND Reference | Mandatory low-inductance ground connection; minimizes clamping impedance during ESD events |
| 6 | I/O Line 4 | Protected bidirectional data line; connected internally to cathode of D4 and anode of D8 |
Key Features
| Feature | Design Value |
|---|---|
| Four-line ESD protection in one package | Reduces BOM count and PCB footprint vs. discrete diode solutions |
| Low I/O-to-I/O capacitance | 1.5 pF max enables use on USB 2.0 (480 Mbps) and fast I²C (1 MHz+) interfaces |
| VCC-biased clamping configuration | Lowers effective diode capacitance and improves high-frequency response |
| JEDEC-compliant ESD robustness | Class 3B HBM (8 kV) and Class C MM (400 V) ensure reliability in manufacturing and end-use |
| TSOP-6 footprint compatibility | Enables drop-in replacement for other 6-pin ESD arrays without layout redesign |
Applications
| USB 2.0 Data Line Protection | I²C Bus Protection |
|---|---|
Use Scenario: Protecting D+ and D− lines of USB 2.0 host/device ports against ESD during hot-plug events. IC Role / Device Role / Timing Role: Steering diode array that clamps transients to VCC or GND before they reach the USB transceiver. Use Value: Maintains 480 Mbps signaling integrity with <1.5 pF interline capacitance and <1.25 V clamping at 150 mA. | Use Scenario: Safeguarding SDA/SCL lines in microcontroller-based sensor nodes and PMIC communication interfaces. IC Role / Device Role / Timing Role: Low-capacitance transient suppressor placed directly at connector or IC pins to prevent bus lockup. Use Value: Enables reliable 1 MHz I²C operation with <3.0 pF I/O-to-GND loading and −40°C to +85°C functional range. |
| T1/E1 Secondary IC Protection | Video Line Protection |
Use Scenario: Shielding line driver/receiver ICs in telecom access equipment from induced surges on T1/E1 twisted-pair interfaces. IC Role / Device Role / Timing Role: Four-channel ESD clamp referenced to local ground or bias rail, integrated near connector entry point. Use Value: Delivers IEC61000−4−2 Level 4 immunity while adding <0.5 mm² PCB area vs. discrete TVS solutions. | Use Scenario: Guarding analog video inputs (e.g., CVBS, YPbPr) in set-top boxes and display controllers against handling ESD. IC Role / Device Role / Timing Role: Low-leakage (≤50 µA @ 70 V) diode array preserving DC-coupled signal path integrity. Use Value: Prevents pixel noise or sync loss by limiting transient overshoot to <1.25 V with minimal capacitive loading. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD4E001DRYR | Lower I/O-to-I/O capacitance (0.7 pF typ), higher RJA (620 °C/W), same TSOP-6 package | Better suited for >1 Gbps differential interfaces; less margin for high-energy transients | Prefer when signal bandwidth exceeds USB 2.0; verify thermal derating for repeated surges |
| SZ1.5SMC15AT3G | Discrete unidirectional TVS (15 V VBR), higher capacitance (>100 pF), DO-214AB package | Designed for power-rail clamping-not data-line protection; unsuitable for high-speed signals | Only applicable for supply rail protection; not a functional substitute for NUP4304MR6T1's four-line I/O architecture |
Compared with TPD4E001DRYR and SZ1.5SMC15AT3G, the NUP4304MR6T1 uniquely balances low interline capacitance, integrated four-line topology, and proven IEC61000−4−2 Level 4 performance in a compact TSOP-6 footprint-making it optimal for space-constrained, multi-line interface protection where signal fidelity and board area are critical.
Availability
NUP4304MR6T1 is available at Aetrix Electronics and suitable for USB 2.0 interface protection, I²C bus hardening, and telecom secondary IC safeguarding requiring stable component supply across production lifecycles.
Supply support for NUP4304MR6T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The NUP4304MR6T1 belongs to onsemi's MicroIntegration™ ESD protection portfolio, engineered specifically for high-speed digital interface protection where low capacitance, small footprint, and system-level ESD compliance are mandatory.
FAQ
What is the maximum I/O-to-I/O capacitance specification for NUP4304MR6T1?
The NUP4304MR6T1 has a maximum I/O-to-I/O capacitance of 1.5 pF at 0 V and 1 MHz, measured per diode pair. This value is critical for maintaining signal integrity on high-speed interfaces like USB 2.0 and fast-mode I²C. The typical value is 0.8 pF, and the measurement condition is explicitly defined in the official onsemi datasheet Rev. 1 (January 2006), Section "ELECTRICAL CHARACTERISTICS".
Can NUP4304MR6T1 be used without connecting pin 2 (VCC)?
Yes, NUP4304MR6T1 supports unbiased operation (Option 4 in the datasheet), where pin 2 is left unconnected or tied to an external TVS diode for reference. In this mode, clamping occurs at VF + VTVS, and I/O-to-GND capacitance increases slightly versus biased operation. The NUP4304MR6T1 remains fully functional for ESD protection but with higher effective capacitance than when VCC bias is applied.
What is the recommended PCB layout practice for grounding pin 5 of NUP4304MR6T1?
Pin 5 (GND) of the NUP4304MR6T1 must connect directly to a low-inductance ground plane using multiple short vias-trace length should be minimized to avoid impedance that degrades ESD clamping performance. The onsemi datasheet emphasizes that long or narrow ground traces increase parasitic inductance, raising clamping voltage during transients. For optimal NUP4304MR6T1 performance, dedicate ≥2 mm² of continuous copper under the TSOP-6 pad and use ≥3 thermal vias to inner ground layers.
Does NUP4304MR6T1 meet IEC61000−4−2 Level 4 for both contact and air discharge?
Yes, the NUP4304MR6T1 is rated for IEC61000−4−2 Level 4: 8 kV contact discharge and 15 kV air discharge. This certification is confirmed in the "Features" section and "APPLICATIONS INFORMATION" of the official onsemi datasheet (NUP4304MR6/D, Rev. 1). The device achieves this through its integrated steering diode architecture and optimized junction design, making it suitable for end-equipment requiring full compliance with international ESD immunity standards.
What is the peak forward surge current rating for NUP4304MR6T1?
The NUP4304MR6T1 has a peak forward surge current rating of 500 mA for a single non-repetitive event. This value is specified under "MAXIMUM RATINGS" in the datasheet as IFM(surge). It reflects the device's ability to safely divert a single ESD pulse without degradation, distinct from its 450 mA repetitive peak forward current (IFRM) and 2.0 A non-repetitive surge at t = 1.0 s. Designers must ensure transient energy stays within this limit for reliable NUP4304MR6T1 operation.
NUP4304MR6T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SC-74, SOT-457
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Steering (Rail to Rail)
- Unidirectional Channels:
- 4
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- -
- Voltage - Breakdown (Min):
- 70V
- Voltage - Clamping (Max) @ Ipp:
- -
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- 1.6pF @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-74
NUP4304MR6T1 FAQ
1.How can I place an order for NUP4304MR6T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for NUP4304MR6T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NUP4304MR6T1 reliable?
The price and inventory of NUP4304MR6T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NUP4304MR6T1 is usually 5 days.
3.What payment methods are accepted for NUP4304MR6T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NUP4304MR6T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NUP4304MR6T1?
NUP4304MR6T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NUP4304MR6T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NUP4304MR6T1?
For technical support, including NUP4304MR6T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NUP4304MR6T1 requirements.
6.How does Aetrix verify that NUP4304MR6T1 is sourced from the original manufacturer or authorized distributors?
All NUP4304MR6T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NUP4304MR6T1 meets industry standards.
7.What is the process for return or replacement of NUP4304MR6T1?
All NUP4304MR6T1 units undergo pre-shipment inspection (PSI). If there is an issue with NUP4304MR6T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NUP4304MR6T1 part is unused and in its original packaging.
Return procedure for NUP4304MR6T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NUP4304MR6T1 Tags

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ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

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ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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