onsemi PACDN042YB3R
- Part No.:
- PACDN042YB3R
- Manufacturer:
- onsemi
- Category:
- TVS Diodes
- Package:
- SC-70, SOT-323
- Datasheet:
-
PACDN042YB3R.pdf
- Description:
- TVS DIODE 5.5VWM 8VC SC70-3
- Quantity:
- Payment:

- Shipping:

Inventory:7,561
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Product details
Overview
PACDN042YB3R from onsemi is a 3-pin SC-70 ESD protection diode array designed for low-capacitance, high-reliability transient suppression on signal lines. It delivers ±20 kV IEC 61000-4-2 contact ESD protection, 5.5 V reverse stand-off voltage, 30 pF capacitance at 2.5 VDC/1 MHz, and clamps to ≤6.8 V (positive) and ≥−1.2 V (negative) at 10 mA, making it suitable for USB 2.0 data line protection in portable electronics.
For engineers reviewing the PACDN042YB3R datasheet, pinout, applications, or equivalent options, key selection criteria include its SC-70-3 package footprint, dual-cathode/GND terminal configuration, low-leakage performance (<100 nA at 5 V), and compatibility with space-constrained high-speed interface layouts requiring sub-35 pF parasitic capacitance.
Technical Context
The PACDN042YB3R implements a dual-channel unidirectional ESD protection architecture with two independent cathodes referenced to a common GND terminal. Its internal structure uses silicon avalanche diodes optimized for fast response (<1 ns) to ESD transients while maintaining low dynamic resistance (1.0 Ω forward, 1.4 Ω reverse) under surge conditions.
It operates across −40 °C to +85 °C and supports system-level IEC 61000-4-2 Level 4 compliance without external components. The device is Pb-free, RoHS-compliant, and rated for 3000 units per tape-and-reel shipment - consistent with standard SC-70 handling and reflow profiles.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ESD Rating | ±20 kV contact discharge per IEC 61000-4-2 - ensures robust immunity against user-handling ESD events on exposed ports. |
| Reverse Stand-off Voltage | 5.5 V min - defines maximum continuous operating voltage before conduction begins; compatible with 5 V and 3.3 V logic rails. |
| Clamp Voltage (Positive) | 6.8 V max at 10 mA - limits peak transient voltage seen by downstream ICs during ESD strike. |
| Clamp Voltage (Negative) | −1.2 V min at −10 mA - prevents negative overvoltage damage to input structures of CMOS receivers. |
| Capacitance | 30 pF typ at 2.5 VDC/1 MHz - enables use on USB 2.0 (480 Mbps), UART, and other <100 Mbps interfaces without signal integrity degradation. |
| Leakage Current | 100 nA max at 5 V - minimizes standby power loss and avoids false triggering in high-impedance sensing nodes. |
| Package | SC-70-3 (Case 419AB) - 1.25 mm × 2.0 mm footprint with 0.65 mm pitch; supports automated SMT assembly and dense PCB layouts. |
Pinout & Package
SC-70-3 package (Case 419AB), 1.25 mm × 2.0 mm body, 0.65 mm lead pitch, 0.9 mm max height. Compliant with JEDEC MO-203.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode | ESD protection node for first signal line; connects directly to protected trace (e.g., USB D+). |
| 2 | GND | Common anode reference for both diodes; must be connected to low-inductance system ground plane. |
| 3 | Cathode | ESD protection node for second signal line; connects directly to protected trace (e.g., USB D−). |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel unidirectional ESD protection | Two independent cathodes share one GND terminal - simplifies layout and reduces component count vs. discrete diodes. |
| Low 30 pF capacitance | Preserves signal rise/fall times on high-speed digital lines up to 480 Mbps without added jitter or attenuation. |
| ±20 kV IEC 61000-4-2 contact rating | Exceeds industrial and consumer ESD immunity requirements without derating or additional staging. |
| Sub-100 nA leakage at 5 V | Enables direct placement on battery-powered sensor inputs and always-on wake-up lines without measurable current drain. |
| Pb-free / RoHS-compliant construction | Meets global environmental regulations and supports lead-free reflow soldering (J-STD-020 compliant). |
Applications
| USB 2.0 Interface Protection | Industrial Serial Port Protection |
|---|---|
Use Scenario: Protecting D+ and D− lines of USB 2.0 host/device connectors in handheld test equipment. IC Role / Device Role / Timing Role: Bidirectional transient voltage suppressor placed immediately at connector entry point. Use Value: Prevents latch-up or gate oxide damage in USB transceivers during field ESD events while adding <0.1 dB insertion loss at 240 MHz. |
Use Scenario: Shielding RS-232/RS-485 transceiver pins in factory-floor PLC I/O modules exposed to maintenance personnel contact. IC Role / Device Role / Timing Role: Front-end ESD clamp on driver/receiver signal paths before level-shifting circuitry. Use Value: Maintains signal integrity over 25 m cable runs by limiting transient-induced overshoot to <7 V peak, avoiding false edge detection. |
| Consumer Audio Jack Protection | Automotive Infotainment Data Lines |
Use Scenario: Safeguarding 3.5 mm audio jack mic/line-in pins in Bluetooth speakers subjected to repeated plug/unplug cycles. IC Role / Device Role / Timing Role: Low-capacitance shunt protector on analog input paths upstream of ADC front-end. Use Value: Adds only 30 pF loading to AC-coupled audio path, preserving frequency response flatness to 20 kHz with no audible distortion. |
Use Scenario: Protecting I²C and UART lines between head unit MCU and touch display controller in automotive dashboards. IC Role / Device Role / Timing Role: System-level ESD guard on low-voltage bidirectional buses operating at 3.3 V. Use Value: Enables compliance with ISO 10605 (±15 kV air/±8 kV contact) without altering bus timing margins or requiring pull-up resistor derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPD2E001DRSR | Single-channel, 0.5 pF typical capacitance, 5.5 V stand-off, SC-70-3 package. | Optimized for ultra-high-speed interfaces (e.g., HDMI, PCIe); lacks dual-channel integration. | Select when protecting individual high-frequency lines where <1 pF loading is mandatory and board space allows separate devices per line. |
| ESD5Z3.3T5G | Single-channel, 3.3 V stand-off, 15 pF capacitance, SOD-523 package. | Lower stand-off voltage suits 3.3 V-only systems; smaller footprint but higher thermal impedance. | Choose for cost-sensitive 3.3 V embedded designs where dual-line coordination is unnecessary and 15 pF capacitance is acceptable. |
Compared with TPD2E001DRSR and ESD5Z3.3T5G, PACDN042YB3R provides integrated dual-line protection in a single SC-70-3 package with balanced 5.5 V stand-off and 30 pF capacitance - ideal for differential pairs like USB 2.0 where channel matching and layout symmetry are critical.
Availability
PACDN042YB3R is available at Aetrix Electronics and suitable for USB interface protection, industrial serial port hardening, and consumer audio jack safeguarding requiring stable component supply and full RoHS compliance.
Supply support for PACDN042YB3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power management, analog, sensors, and ESD protection solutions for automotive, industrial, and consumer markets.
The PACDN042 family targets compact, high-reliability ESD protection for differential and single-ended signal lines in portable and space-constrained electronics - emphasizing low capacitance, high surge tolerance, and seamless SMT integration.
FAQ
What is the primary function of the PACDN042YB3R?
The PACDN042YB3R is a dual-channel unidirectional ESD protection diode array in SC-70-3 package. Its primary function is to clamp transient voltages induced by electrostatic discharge on two signal lines-such as USB D+ and D−-to safe levels before they reach sensitive downstream ICs. Each cathode pin connects to a protected line, while the GND pin serves as the common anode return path. This design ensures coordinated protection without cross-talk or timing skew between channels.
Does the PACDN042YB3R support bidirectional signal lines like USB?
Yes, the PACDN042YB3R supports bidirectional signal lines such as USB 2.0 differential pairs. Although internally unidirectional (cathode-to-GND), its dual-cathode configuration allows symmetric placement on both D+ and D− traces. During positive transients, each diode clamps to ~6.8 V; during negative transients, it conducts to ~−1.2 V - effectively limiting excursion in both directions without rectifying or distorting the AC-coupled data waveform. This behavior is validated per IEC 61000-4-2 testing protocols.
What is the maximum operating temperature range for PACDN042YB3R?
The PACDN042YB3R is specified for continuous operation from −40 °C to +85 °C, as defined in Table 3 of its datasheet. This range covers standard commercial and extended industrial environments. The device maintains full ESD protection performance-including ±20 kV contact discharge capability and 30 pF capacitance-across this entire temperature span. Derating is not required within these limits, and thermal shutdown or parametric drift is not observed under normal operating conditions.
Can PACDN042YB3R replace discrete 1N4148 diodes for ESD protection?
No, PACDN042YB3R is not a functional replacement for 1N4148 diodes. While both are silicon diodes, the PACDN042YB3R is engineered specifically for ESD suppression: it features optimized junction geometry for low dynamic resistance (1.0 Ω forward), precise clamping thresholds (5.5 V stand-off), and guaranteed ±20 kV IEC 61000-4-2 performance. A 1N4148 lacks controlled breakdown characteristics, exhibits higher leakage (>1 µA), and offers no certified ESD rating - making it unsuitable for reliable system-level ESD protection per international standards.
Is PACDN042YB3R pin-compatible with other members of the PACDN042–PACDN046 family?
No, PACDN042YB3R is not pin-compatible with other family members. PACDN042YB3R uses SC-70-3 (3-pin), whereas PACDN044Y5R is SOT-23-5, PACDN045Y6R is SOT-23-6, and PACDN043Y4R is SOT-143. Pin count, pinout, and package dimensions differ across variants - for example, PACDN042YB3R has Cathode-GND-Cathode arrangement, while PACDN044Y5R uses a 5-pin configuration with multiple GND and cathode terminals. Interchange requires PCB redesign and layout verification.
PACDN042YB3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- SC-70, SOT-323
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Zener
- Unidirectional Channels:
- 2
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 5.5V
- Voltage - Breakdown (Min):
- 6.2V
- Voltage - Clamping (Max) @ Ipp:
- 8V
- Current - Peak Pulse (10/1000µs):
- -
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- General Purpose
- Capacitance @ Frequency:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-3
PACDN042YB3R FAQ
1.How can I place an order for PACDN042YB3R through Aetrix?
Please submit a Request for Quotation (RFQ) for PACDN042YB3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PACDN042YB3R reliable?
The price and inventory of PACDN042YB3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PACDN042YB3R is usually 5 days.
3.What payment methods are accepted for PACDN042YB3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PACDN042YB3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PACDN042YB3R?
PACDN042YB3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PACDN042YB3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PACDN042YB3R?
For technical support, including PACDN042YB3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PACDN042YB3R requirements.
6.How does Aetrix verify that PACDN042YB3R is sourced from the original manufacturer or authorized distributors?
All PACDN042YB3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PACDN042YB3R meets industry standards.
7.What is the process for return or replacement of PACDN042YB3R?
All PACDN042YB3R units undergo pre-shipment inspection (PSI). If there is an issue with PACDN042YB3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PACDN042YB3R part is unused and in its original packaging.
Return procedure for PACDN042YB3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PACDN042YB3R Tags

-
ESD9B5.0ST5G
onsemi

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DESD3V3E1BL-7B
Diodes Incorporated

-
ESD5Z3.3T1G
onsemi

-
D5V0H1B2LP-7B
Diodes Incorporated

-
D5V0P1B2LP-7B
Diodes Incorporated

-
DESD5V0U1BA-7
Diodes Incorporated

-
ESD5Z5.0T1G
onsemi

-
DESD5V0U1BB-7
Diodes Incorporated

-
D12V0L1B2LP-7B
Diodes Incorporated

-
PESD2V0Y1BSFYL
Nexperia USA Inc.

-
DF2S5M4CT,L3F
Toshiba Semiconductor and Storage

-
D5V0L1B2WS-7
Diodes Incorporated
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