Nexperia USA Inc. PESD1IVN24-LSYL
- Part No.:
- PESD1IVN24-LSYL
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SOD-882
- Datasheet:
-
PESD1IVN24-LSYL.pdf
- Description:
- TVS DIODE 24VWM 42VC DFN1006BD-2
- Quantity:
- Payment:

- Shipping:

Inventory:15,978
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Product details
Overview
PESD1IVN24-LSYL from Nexperia is a bidirectional automotive-grade ESD protection diode in DFN1006BD-2 (SOD882BD) package, designed for transient suppression on in-vehicle network lines. It delivers 24 V reverse standoff voltage, 33 V clamping at 3.5 A, 30 kV IEC 61000-4-2 ESD immunity, <1 nA leakage, and 14 pF capacitance-enabling robust protection of CAN, LIN, FlexRay, and SENT bus interfaces.
For engineers reviewing the PESD1IVN24-LSYL datasheet, PESD1IVN24-LSYL pinout, PESD1IVN24-LSYL application, or PESD1IVN24-LSYL equivalent, key selection criteria include automotive AEC-Q101 qualification, side-wettable flanks for solder joint inspection, dual-cathode configuration for bidirectional line protection, and ultra-low capacitance for high-speed bus integrity.
Technical Context
This device implements a dual-cathode, bidirectional TVS structure optimized for automotive IVN buses. Its clamping behavior is characterized by 33 V typical at 3.5 A (8/20 µs), with dynamic resistance of 0.2 Ω and breakdown voltage ranging from 25.5 V to 35.5 V at 10 mA.
The DFN1006BD-2 package features side-wettable flanks for automated optical solder-joint inspection and supports reflow-compatible footprint per Nexperia's SOD882BD layout guidelines. It operates across –55 °C to +150 °C ambient and junction temperatures, meeting AEC-Q101 Grade 3 requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 24 V - Maximum continuous operating voltage before conduction begins; ensures no interference during normal bus signaling. |
| Clamping Voltage | 33 V (typ) at 3.5 A - Peak voltage seen by protected IC during surge; keeps downstream transceivers within safe operating limits. |
| ESD Rating | 30 kV per IEC 61000-4-2 & ISO 10605 - Validated immunity to contact discharge events common in vehicle assembly and service environments. |
| Diode Capacitance | 14 pF (typ) at 0 V - Low enough to avoid signal integrity degradation on 1 Mbps CAN or 20 kbps LIN lines. |
| Leakage Current | <1 nA at 24 V - Negligible standby power draw and minimal impact on bus biasing networks. |
| Package | DFN1006BD-2 (SOD882BD) - 1.0 mm × 0.6 mm × 0.47 mm body with side-wettable flanks for AOI-capable solder joint verification. |
Pinout & Package
DFN1006BD-2 (SOD882BD) is a 2-terminal leadless plastic package with side-wettable flanks, 0.65 mm pitch, and 1 mm × 0.6 mm footprint. The marking bar indicates cathode orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Cathode (Diode 1) | Forms first half of bidirectional clamping path; connects to protected line (e.g., LIN_H or CAN_H). |
| 2 | Cathode (Diode 2) | Completes bidirectional structure; connects to same protected line, enabling symmetrical ±30 kV ESD handling. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 Qualified | Validated for automotive Grade 3 (–40 °C to +125 °C ambient) operation and reliability under thermal cycling, humidity, and mechanical stress. |
| Side-Wettable Flanks | Enables automated optical inspection (AOI) of solder joints without X-ray, reducing manufacturing defect escape in high-volume automotive PCB assembly. |
| Bidirectional Clamping | Dual-cathode architecture provides symmetrical protection against both positive and negative transients without polarity dependency on board layout. |
| Low Dynamic Resistance | 0.2 Ω typical - Minimizes voltage overshoot during fast-rising ESD pulses, improving clamping precision and system-level robustness. |
Applications
| CAN Bus Protection | LIN Bus Protection |
|---|---|
Use Scenario: Protecting high-speed Controller Area Network (CAN) transceivers in engine control units, ADAS domain controllers, and body electronics modules. IC Role / Device Role / Timing Role: Bidirectional transient suppressor placed between connector and CAN transceiver input pins (CAN_H/CAN_L). Use Value: Maintains signal integrity up to 1 Mbps while limiting ESD-induced latch-up or damage to transceivers during vehicle assembly or field service. | Use Scenario: Safeguarding low-speed Local Interconnect Network (LIN) slave nodes in door modules, seat controls, and climate actuators. IC Role / Device Role / Timing Role: Line protector mounted directly at the LIN connector, shunting transients before they reach the LIN transceiver or microcontroller GPIO. Use Value: Enables reliable 20 kbps communication with <1 nA leakage, avoiding false wake-ups or bus contention in battery-sensitive applications. |
| FlexRay Bus Protection | SENT Sensor Interface Protection |
Use Scenario: Shielding FlexRay physical layer components in chassis and powertrain systems requiring deterministic 10 Mbps communication. IC Role / Device Role / Timing Role: ESD guard on differential FlexRay A/B lines, positioned adjacent to the connector to minimize inductance in the transient return path. Use Value: Preserves signal edge fidelity and timing margin with 14 pF capacitance, preventing bit errors caused by ESD-induced jitter or overshoot. | Use Scenario: Securing Single Edge Nibble Transmission (SENT) sensor outputs in engine pressure, temperature, and position sensing circuits. IC Role / Device Role / Timing Role: Point-of-entry protector on the SENT signal line between analog sensor and microcontroller ADC input. Use Value: Prevents ESD-induced data corruption or ADC saturation while adding negligible loading (<1 nA leakage) to the open-drain SENT output stage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESDALC6V1-1U2 | Lower VRWM (6.1 V), higher capacitance (100 pF), same AEC-Q101 Grade 3 | Targeted at lower-voltage interfaces (e.g., USB, I²C); unsuitable for 24 V IVN buses | Select only for sub-12 V signal lines where clamping voltage must be below 12 V. |
| TPD2E001DRYR | 2-channel unidirectional, 5.5 V VRWM, 12 pF, non-AEC-Q101 | Designed for consumer port protection; lacks automotive qualification and 24 V standoff capability | Acceptable for non-automotive prototypes but not for production automotive ECUs. |
Compared with ESDALC6V1-1U2 and TPD2E001DRYR, PESD1IVN24-LSYL uniquely combines 24 V standoff, 30 kV ESD rating, AEC-Q101 Grade 3 compliance, and 14 pF capacitance-making it the only validated solution for protecting 12–24 V automotive serial buses without compromising speed or reliability.
Availability
PESD1IVN24-LSYL is available at Aetrix Electronics and suitable for CAN bus design, LIN node integration, and FlexRay interface development requiring stable component supply and full automotive qualification traceability.
Supply support for PESD1IVN24-LSYL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, high-reliability discrete, logic, and MOSFET solutions for automotive, industrial, and computing markets.
PESD1IVN24-LSYL belongs to Nexperia's Automotive ESD Protection portfolio, engineered specifically to meet stringent IVN bus requirements-including bidirectional surge handling, ultra-low capacitance, and AEC-Q101 Grade 3 qualification for under-hood and cabin applications.
FAQ
What is the maximum peak pulse current rating for PESD1IVN24-LSYL?
The rated peak pulse current (IPPM) is 3.5 A under 8/20 µs exponential decay waveform per IEC 61000-4-5. This value is confirmed in Table 1 (Quick reference data) and Table 5 (Limiting values) of the official Nexperia datasheet dated 9 April 2021. It defines the highest transient energy the device can safely clamp without degradation.
Does PESD1IVN24-LSYL support both contact and air-gap ESD testing per IEC 61000-4-2?
Yes, PESD1IVN24-LSYL is rated for 30 kV contact discharge per IEC 61000-4-2, as stated in Section 2 (Features and benefits) and Table 5. While air-gap discharge is not explicitly called out, the 30 kV rating applies to standard IEC 61000-4-2 test conditions including both contact and air-gap methods per the specification's scope.
How does the dual-cathode configuration enable bidirectional protection?
The dual-cathode pinning (Pin 1 = K1, Pin 2 = K2) forms a back-to-back diode structure. When voltage exceeds +24 V on either terminal, one diode conducts to ground; when voltage drops below –24 V, the other diode conducts. This symmetric arrangement provides identical clamping for positive and negative transients without external polarity routing.
Is the DFN1006BD-2 package compatible with standard reflow soldering profiles?
Yes, the DFN1006BD-2 package is qualified for lead-free reflow soldering. Nexperia provides a dedicated footprint (Figure 11) and thermal profile guidance in Section 12 of the datasheet. Side-wettable flanks ensure reliable solder joint formation and enable automated optical inspection without requiring X-ray verification.
PESD1IVN24-LSYL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SOD-882
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 25.5V
- Voltage - Clamping (Max) @ Ipp:
- 42V
- Current - Peak Pulse (10/1000µs):
- 3.5A (8/20µs)
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- CAN
- Capacitance @ Frequency:
- 14pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1006BD-2
PESD1IVN24-LSYL FAQ
1.How can I place an order for PESD1IVN24-LSYL through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD1IVN24-LSYL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD1IVN24-LSYL reliable?
The price and inventory of PESD1IVN24-LSYL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD1IVN24-LSYL is usually 5 days.
3.What payment methods are accepted for PESD1IVN24-LSYL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD1IVN24-LSYL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD1IVN24-LSYL?
PESD1IVN24-LSYL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD1IVN24-LSYL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD1IVN24-LSYL?
For technical support, including PESD1IVN24-LSYL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD1IVN24-LSYL requirements.
6.How does Aetrix verify that PESD1IVN24-LSYL is sourced from the original manufacturer or authorized distributors?
All PESD1IVN24-LSYL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD1IVN24-LSYL meets industry standards.
7.What is the process for return or replacement of PESD1IVN24-LSYL?
All PESD1IVN24-LSYL units undergo pre-shipment inspection (PSI). If there is an issue with PESD1IVN24-LSYL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD1IVN24-LSYL part is unused and in its original packaging.
Return procedure for PESD1IVN24-LSYL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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